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Zephyr

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Antti Lukats edited this page Nov 12, 2018 · 18 revisions

Requirements:

  1. must use 1.13 version without modification to the OS Core
  2. must be able to boot Philosophers and Synchronization
  3. must a run "the provided" zephyr application on target FPGA

Notes:

  1. It is not so clear what is considered OS Core, assume minimal changes are OK
  2. It should be acceptable that Philosophers and Synchronization boot only in verilator
  3. It should be acceptable to provide "LED Blinky" or "Hello World" to run on real hardware
  4. Full PLIC support is not required can be disabled, then machine timer interrupt would be used

Based on FAQ it seems that outputting messages is a requirement (well again not defined if needed on target board).

Implementation

All required applications run easily within 32K shared CODE/DATA memory. SoC requirements for Zephyr are explained in SoC Design wiki page

Files to be added changed:

  1. KConfig and header files for your SoC and UART
  2. UART driver

If you do only the above mentioned changes than you for sure have not modified the OS Core.

Drivers

Timer

Timer Driver should be enabled in

-> Device Drivers -> Timer Drivers
[*] RISCV Machine Timer

If you do not use Machine Timer then you need to provide full PLIC support and external Timer device with its own driver.

Interrupt

PLIC Driver can be disabled in

-> Device Drivers -> Interrupt Controller
[ ] Platform Level Interrupt Controller (PLIC)

Console/Serial

This is not clear form the official rules, being able to boot does not necessarily mean it must provide the console output on UART so it may be acceptable to use RAM console and disable all serial drivers. In such case you still can provide the console output in verilator where you can convert the RAM console STORE instructions to stdout print. Also for Microsemi you may be able to "look" RAM console output in SmartDebug.

An example very simple UART driver is here

https://github.com/micro-FPGA/zephyr/blob/v1.13-branch/drivers/serial/uart_ev.c

This driver would also be compatible with verilator, it basically writes the char for UART transmit to some memory mapped location (defined in soc.h at the moment).

GPIO

Not needed by the rules, could be implemented to deliver LED Blinky Zephyr application as the pre-loaded FPGA demo.

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