FPGA Design

SmartFusion/IGLOO2

Cortex-M3 assisted boot

This boot method is only possible with SmartFusion2 based targets, here example SmartDesign canvas:

FIC is configured as APB3 and connected directly to Dual ported LSRAM port A. LSRAM Port B is exported from smartdesign. Ready control should be implemented it takes a few LUT (only needed if you want to read the RAM from Cortex-M3).

Then in your toplevel you have verilog code:

ev_boot ev_boot_0 (
    .CLK1_PAD (SYSCLK),   // Clock from External Pin
    .DEVRST_N (RESET_N),  // Reset from External Pin
     // LSRAM memory interface
    .B_WEN    (WEN),      // Write enable
    .B_DIN    (DIN),      // Data to LSRAM block
    .B_ADDR   (ADDR),     // Address to LSRAM block
    .B_DOUT   (DOUT),     // Data out from initialized RAM

    .cpu_clk  (CLK_OUT)   // Clock to SoftCPU from PLL
);

From here you can continue to write your verilog code. Of course Cortex-M3 must make "memcopy" at startup to copy your RISCV Code from eNVM into your LSRAM Block.

Note: this is only as "example" - the DP RAM Generator does not generate byte enables, so the example only can write full 32 bits.

For the SoC resource utilization there are extra 34 LUT involved, coming from the SmartDesign MSS Block.

This LSRAM Block is accessible from Cortex-M3 and from your SoftCPU, if you want you can make firmware for Cortex-M3 that polls some RAM location, and forwards that to the MSS UART that you wire via fabric to external UART pins. Then you do not need to implement UART in your HDL code. This should be acceptable advanced use. Cortex-M3 would work as "smart peripheral".

iCE40 Ultra Plus

You can use EBR based initialized memory during initial development then you do not need to start writing bootstrap immediately. Only Dhrystone and Philosophers are so big that they do not fit to EBR at all and bootstrap (or XiP from SPI) is needed. Synchronization may fit to EBR.