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FAQ
Proposed resource calculation: include only Logic Elements (max (LUT,FF) as long as RAM utilization can be considered as balanced. If RAM resources are used too heavily then OVER_UTILIZATION_RATIO (0%, 10%,..,100%) should be assigned and the final resources would be calculated as:
single_resource_metrics = max(LUT,FF) + OVER_UTILIZATION_RATIO * (number_of_bits_in_used_small_ram_prims/16)
where number_of_bits_in_used_small_ram_prims is number of primitive bits - total per primitive not bits used within primitive. Parity bits in Microsemi should be excluded.
Large memories (eSRAM, SPRAM) should be counted differently, proposed: eSRAM=0, SPRAM=0 as long as maximum 2 SPRAM's are used. If more than 2 SPRAM are used a fixed cost could be added.
Math blocks should be counted as 0 or 1 LUT cost per DSP primitive.
Reason 1: use of Math blocks does not provide any benefit on Microsemi, and very small benefit on iCE40. Explanation: small design would not implement mul-div and would not benefit from math block being used as multiplier. The only gain in LUT from the use of math block would be implementing addsub on Lattice (on Microsemi the fixed price of 36 LUT is already too high).
Reason 2: RAM blocks are needed to hold the applications, and those should not be counted. On Microsemi each uSRAM and LSRAM has already a fixed cost of 36 LUT.
RAM Price = 0 LUT
| Type | Actual Price | Comment |
|---|---|---|
| uSRAM | 36 | fixed cost |
| LSRAM | 36 | fixed cost |
| eSRAM | 0 | + AHB overhead |
| eNVM | 0 | ROM not RAM? |
| EBR | 0 | |
| SPRAM | 0 |
RAM Price = 1 LUT per primitive
| Type | Actual Price | Comment |
|---|---|---|
| uSRAM | 37 | fixed cost |
| LSRAM | 37 | fixed cost |
| eSRAM | 1 | + AHB overhead |
| eNVM | 1 | ROM not RAM? |
| EBR | 1 | |
| SPRAM | 1 |
Note: eSRAM can be considered as 2 blocks, but this is not visible in the resource utilization reports!
RAM Price = bit-width x LUT per primitive
| Type | Actual Price | Comment |
|---|---|---|
| uSRAM | 54 | fixed cost |
| LSRAM | 54 | fixed cost |
| eSRAM | 64 (128?) | + AHB overhead |
| eNVM | 64 | ROM not RAM? |
| EBR | 16 | |
| SPRAM | 16 |
At the end of Reports in Libero there is file your_topname_layout_log.log at the end of this file there is LE count:
| Type | Used | Total | Percentage |
|---|---|---|---|
| 4LUT | 72 | 12084 | 0.60 |
| DFF | 75 | 12084 | 0.62 |
| I/O Register | 0 | 579 | 0.00 |
| Logic Element | 75 | 12084 | 0.62 |
Only the used count of "Logic Element" is used for Logic Elements metrics.
Lattice:
Radiant only provide LE(Estimated) number, so for the Logic Elements please use
max(LUT, FF)
Contest rules actually do not force use of specific boards, the rules say "have option" and "can be used", not that boards listed have to be used. So you could use any board that targets SmartFusion2, IGLOO2 or iCE40 Ultra Plus. Similarly a good layer would say that using "smaller" devices like M2S010 or UP3K would also be acceptable. You should however not use devices larger than M2GL025/M2S025. You should not expect to get extra points if you target device smaller than on the boards suggested by the contest. You should not expect extra points if you design your own board for the contest and run the SoftCPU on that board, but you could that.
The SoftCPU does not need to have any debug capabilities. Should they be there, they can be disabled.
There are 55 tests defined, they all must pass and they all must produce correct signature. As riscv official documents to not define the verification using other means as by signature check, we must provide designs that can be used to run the tests and to produce those signatures for the judges to verify. If we want to qualify in full then we must provide the signature creation capabilities both on verilator testbench as on real hardware running on defined platforms we are targeting.
More in RV32I-Compliance
Microsemi Fabric memories are not initialized, would LUTROM based bootrom count in resource utilization?
Yes. You should count that the logic utilization report from Libero is taken "AS IS" and the bootrom LUT's will not be excluded.
Yes, resource utilization is counted for ready to run full SoC implementation for the target FPGA.
No, as in that case it would not be possible to verify that the sources comply to the licensing terms.
No, it should be possible to recompile all source code using tools available to anyone without extra cost.
As minimum a transmit only UART function and Machine Timer generating interrupt are needed. More in Soc Design
It may also be acceptable that you do not provide UART function in the FPGA and only SoC peripheral is single bit GPIO to demonstrate Zephyr Blinky on the target Hardware. Tests requiring UART would then be run only in verilator where testbench code can capture a memory write as UART output. As per offical FAQ published October 26 means of "outputting messages" is needed - it is still unclear if Morse code on LED is acceptable for target boards with no UART. Using external USB TTL UART is acceptable, in that case instructions should be given how to connect it to the target board.
This can be answered that doing minimal changes by adding KConfig/header for your SoC and only adding UART driver you are not modifying the core. Adding support for non standard interrupt handling to support as example picorv32 could be considered as changes to the core, the final decision would be by the judges.