Smallest Design

Lattice UP5K

Minimal FPGA RAM use would be 1 EBR and 1 SPRAM (only 1 SPRAM is possible but not so meaningful)

Bootstrap from UART or SPI is needed unless the SoftCPU implements XiP from SPI Flash.

Note for SPI Flash users: iCE40 places the SPI Flash into deep powerdown - it is necessary to send 0xAB command to wake it up. This feature can be disable when iCecube2 is used, with radiant the seems to be not available.

Microsemi

Minimal FPGA RAM use would be 2 uSRAM (zero fabric RAM use is possible but not so meaningful)

eNVM and eSRAM would not count as FPGA RAM resources as they are not part of FPGA logic at least in SmartFusion2 where they are directly excluded from FPGA fabric resources. For IGLOO2 those resources are however counted as FPGA (or generic) resources.

The scoring is not clear but most likely a design with smallest LE use and reasonable use of uSRAM/LSRAM would still win. Please note that in case eNVM/eSRAM are used you must also provide your verilog models for them under BSD/Apache license for verification with verilator.

Math Block Use

For the smallest design multiply is not needed so the only use of DSP blocks would be LUT saving when implementing an ADD or COUNTER, but each instance of DSP consumes 36 LUT while 32 bit counter without DSP takes 34 LUT.

So smallest design would not benefit from the use of DSP, no matter if there is "LUT price" set on Math Blocks.