SoC Design

Official rules to not say anything at all about the SoC design or required infrastructure, this information has to be gathered from the overall requirements.

Complete list of minimal SoC requirements per rules

Resource	Requirement
User IO	LED * note 1
Code memory	>16K # note 2
Data memory	tbd
Total Memory	32KByte * note 3

Note 1: On Microsemi we could even forget the LED and say that SmartDebug should be used to monitor the SoC output, this would be valid by the rules.

Note 2: Dhrystone compiled with -march=rv32i -mabi=ilp seems to produce over 16K, RV32IM may go just below 16K

Note 3: Minimum memory footprint is 32KByte when using power of 2, the size could be tuned lower to about 28K when using the FPGA RAM primitives directly.

User IO

From minimum requirements a complete design with "some" Zephyr application must be provided to be able to run on the selected FPGA target board. This could be Zephyr Blink LED as the rules do not say that Philosophers or Synchronization FPGA images have to be supplied. This would allow Zephyr testing on the first board suggested by the rules

http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40UltraPlusBreakoutBoard

that board has no console so only user IO is a LED, this would be all that is needed.

So if we take the rules very strictly then the minimum requirement for user IO is single LED. We can always emulate UART console by sending Morse code to the LED. This would be acceptable by the rules. We can also blink the RV32I compliance test signatures using Morse code, this would be acceptable as well.

You could connect upper bit of program counter to LED and let the address decoder to wrap (mirror code space), this would give an almost 0 LUT LED GPIO.

Memory

We must provide enough memory to boot Dhrystone, Philosophers and Synchronization applications. We are a bit constrained by the rules in the regard of Dhrystone compiler and library optimization, but for Zephyr we can take all measures we want to decrease the memory requirement. From the compiler results so far it does not seem possible that those applications compile into total memory footprint under 16K Byte. The actual minimum code+data is less than 32K in all cases. This amount of memory must be accessible to the CPU.

We could make a case saying that the SoC runs on FPGA only Zephyr Blinky as required by the rules, and boots other tests and applications in verilator only with increased memory footprint as Philosophers boot is required on the SoftCPU only by the rules and not directly on the target FPGA board. But this is really narrow path better not be taken, so we should better have the same amount of memory in the FPGA implementation and verilator.

SoC boot Microsemi

SoC boot on Lattice

Options for Application boot:

1. UART bootloader
2. SPI Bootloader
3. XiP from SPI Flash

Placing all code in EBR is not an option as the total memory is less than 16K and we need more than 16K to start Dhrystone. So we must provide either a bootloader or execute in place from external SPI flash.