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Welcome to the wiki for RISC-V Contest 2018

Global scoring

Design	M/S	L/S	M/F	L/F	Extra	Total	Notes
spinalHDL	?	?	50	50	?	100+
engine-V	50	50	0	0	?	100+
reindeer	?					60+
SERV	na	na	na	na	?	?	Special Prize

Smallest Lattice

Design	LC/FabLUT	DSP	EBR	SPRAM	Boot
engine-V	307/280	0	4	1	SPI bootstrap
SERV	?/460+	0	?	?	?
spinalHDL	1610	0	4	2	SPI XiP
fwrisc	1653/?	0	4	?	?

Smallest Microsemi

Design	LE/FabLUT	DSP	SRAM u/L/e	eNVM	Boot
engine-V	346/268	0	1/1/0.4	+	M3
fwrisc	?/1060	0	2/0/?	?	?

LE is Logic Elements FabLUT is actual number of LUT's used (excludes Interface LUT's)

Fastest Lattice

Design	Dhrystone	DMIPS	CPU MHz	DMIPS/MHz
spinalHDL			26?	1.27
Reindeer	10704		24

Fastest Microsemi

Design	Dhrystone	DMIPS	CPU MHz	DMIPS/MHz
spinalHDL			114	1.3
Reindeer	81967		160

List of github entries

• Pulserain Reindeer
• Bitserial RISC-V