Example Lattice
This example implementation uses picorv32 core as "example cpu/soc" - this implementation does not pass all requirements but can be used as getting started design. Initial testing before porting was done with Vivado
\picorv32\scripts\quartus\system.v
was taken as TOP level, then picosoc.v was renamed to early_picosoc.v to make Vivado to include the verilog files in correct order. There is a problem currently that using manual compile order disables RTL modules in Block Design.
LED connected to mem address bit 11, only minimal change in the system.v file was needed.
RV32I Compliance test "I-ADD-01" is executing in simulator, we can see that picorv32 passes the test, the LED will settle down at high level. During the executing we see RAM access activity on the LED.
First try - LED is off? Are clock and reset correct? Adding VIO and ILA.
Clock is running and external Reset from the board is high! And when toggling the reset to picorv32 from VIO it runs the compliance test in FPGA and the LED is lit!
Vivado synthesis did infer correct RAM and loaded the content using verilog $readmem as well.
Taking the exact same verilog files that worked with Vivado in simulation and with real hardware to Lattice Radiant.
The early_picosoc.v renaming trick works here too, using manual compile order is not needed.
Inferring EBR RAM with memory seem to work, up to 8KByte size.
TODO Memory map should be split into RAM with init code (EBR) and RAM (noinit)
Then it would be possible to define EBR RAM in vendor neutral verilog and use $readmem to load the RISCV code.
RAM should be implemented using SPRAM primitives ?
TODO check if inference works for SPRAM (it should actually).
Using U3 FPGA C
| Label | Net | Pin |
|---|---|---|
| OSC_CLK | B3 | |
| LED1 | SPARE_C1 | B1 |
| LED2 | SPARE_C2 | F2 |
| SW6 | SPARE_C3 | C3 |
| SW7 | SPARE_C4 |
Trying to simulate using thee free simulator bundled with Radiant (Aldec), getting as far as:
Error: VCP2000 src/picorv32.v : (1465, 9): Syntax error.
TIP: If you think you need to use simulator for your Lattice optimized version of your SoftCPU make sure Aldec simulator does understands your verilog code.
Attempt to debug with Reveal gets as far as:
ERROR - ERROR: core0 incorrect pattern readout.