A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Vitis_Accel_Examples

Intermediate Language (IL) for Hardware Accelerator Generators

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

Allo: A Programming Model for Composable Accelerator Design

Time-sensitive affine types for predictable hardware generation

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

assorted library of utility cores for amaranth HDL

A new Hardware Design Language that keeps you in the driver's seat

A graph linear algebra overlay

Intel Quartus Prime Synthesis Engine for Docker

HeteroCL-MLIR dialect for accelerator design

Verilog Implementation of Run Length Encoding for RGB Image Compression

上海交通大学软件学院🍭操作系统课程🍦实验

FPGA Hardware Simulation Framework

Příklady ke knize Data, čipy, procesory

A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.

This is BISS-C FPGA IP and It's Driver Repo

FPGA Hardware Simulation Framework