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81 Open 40 Closed
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Issues list

FEEDBACK wires need a default assignment in code bug Something isn't working
#192 opened Mar 17, 2024 by JulianKemmerer
Missing delay for module when looked up by instance name bug Something isn't working
#187 opened Jan 3, 2024 by JulianKemmerer
@JulianKemmerer
Change output directory structure enhancement New feature or request
#183 opened Nov 28, 2023 by JulianKemmerer
Support full C syntax for invoking derived FSMs enhancement New feature or request
#180 opened Sep 17, 2023 by JulianKemmerer
Allow operator overloading to work with derived FSM implementations enhancement New feature or request
#179 opened Sep 17, 2023 by JulianKemmerer
Fix operator overloading to allow use of built in operator in overload bug Something isn't working
#178 opened Sep 17, 2023 by JulianKemmerer
Setup Verilator for multiple clock domain simulations enhancement New feature or request
#176 opened Sep 16, 2023 by JulianKemmerer
Autopipelining that adds IO regs to functions w/ global wires is broken bug Something isn't working
#175 opened Aug 27, 2023 by JulianKemmerer
Upgrade sim to generate clocks in HDL enhancement New feature or request
#174 opened Aug 26, 2023 by JulianKemmerer
Reduce synthesis runs when preparing for pipelining enhancement New feature or request
#173 opened Aug 26, 2023 by JulianKemmerer
Synthesis timing loops (rarely only w/ Vivado so far) bug Something isn't working
#172 opened Aug 15, 2023 by JulianKemmerer
1
Convert sync integer ratio clock crossing c code gen to define struct instead of using fixed size array types enhancement New feature or request
#171 opened Jul 4, 2023 by JulianKemmerer
Enums with shared literal names can cause VHDL syntax errors bug Something isn't working
#168 opened May 27, 2023 by JulianKemmerer
Only 'cpp' for C preprocessing is supported now enhancement New feature or request
#166 opened Feb 15, 2023 by JulianKemmerer
1
Derived FSM style functions have lots of room for optimizations enhancement New feature or request
#163 opened Feb 7, 2023 by JulianKemmerer
2
Union support enhancement New feature or request
#162 opened Feb 6, 2023 by JulianKemmerer
force pipeline stages in for loops enhancement New feature or request
#150 opened Jan 6, 2023 by suarezvictor
2
Global variables of compound types cannot be driven from multiple main functions enhancement New feature or request
#148 opened Nov 23, 2022 by JulianKemmerer
Raw VHDL interface should be bits per stage not slices enhancement New feature or request
#147 opened Nov 11, 2022 by JulianKemmerer
1
Static local variables cannot be declared inside IFs bug Something isn't working
#146 opened Nov 5, 2022 by JulianKemmerer
FIFO_FWFT implementation causes output to pause unexpectedly long after flow control assertion enhancement New feature or request
#142 opened Oct 31, 2022 by JulianKemmerer
2
Loop iterators must be declared outside of the loop bug Something isn't working
#139 opened Oct 28, 2022 by JulianKemmerer
Allowing global variables to be marked as top level clock inputs enhancement New feature or request
#138 opened Oct 27, 2022 by JulianKemmerer
User generated clock wires top level connections are not recognized by all timing tools bug Something isn't working
#137 opened Oct 27, 2022 by JulianKemmerer
2
Reconsider assumption that all 2:1 muxes will have same path delay enhancement New feature or request
#134 opened Oct 22, 2022 by JulianKemmerer
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