Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Upgrade sim to generate clocks in HDL #174

Open
JulianKemmerer opened this issue Aug 26, 2023 · 0 comments
Open

Upgrade sim to generate clocks in HDL #174

JulianKemmerer opened this issue Aug 26, 2023 · 0 comments
Labels
enhancement New feature or request

Comments

@JulianKemmerer
Copy link
Owner

This also makes it easier to support multiple clocks

For Verilator first probably...IIUC this needs newer Verilator than have worked with before

Generate a generic testbench module with clock gen processes that instantiates the top when --sim ?

@JulianKemmerer JulianKemmerer added the enhancement New feature or request label Aug 26, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
enhancement New feature or request
Projects
None yet
Development

No branches or pull requests

1 participant