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33 Open 17 Closed
33 Open 17 Closed
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Issues list

Different spans are printed on Windows vs Linux. This messes with CI. bug Something isn't working
#68 opened Feb 19, 2025 by VonTum
./test.sus_regression appears to be dependent on Operating System. bug Something isn't working
#67 opened Feb 19, 2025 by VonTum
Warn when a state variable is possibly read after possibly being written enhancement New feature or request
#65 opened Feb 18, 2025 by VonTum
ICE when assigning non-gen value to (valid) array access of gen bug Something isn't working ICE Internal Compiler Error
#64 opened Feb 12, 2025 by pbeart
1
std::transmute enhancement New feature or request good first issue Good for newcomers
#61 opened Jan 30, 2025 by VonTum
Module Overloading enhancement New feature or request
#59 opened Jan 30, 2025 by VonTum
Operators should be defined as modules enhancement New feature or request Request Input These are issues about the design of the language, and thus should be discussed
#58 opened Jan 30, 2025 by VonTum
let bindings enhancement New feature or request
#57 opened Jan 29, 2025 by VonTum
Custom compile-time functions (Continuation of #19) enhancement New feature or request Request Input These are issues about the design of the language, and thus should be discussed
#56 opened Jan 29, 2025 by VonTum
4 tasks
Incremental Builds enhancement New feature or request Request Input These are issues about the design of the language, and thus should be discussed
#49 opened Jan 13, 2025 by VonTum
Fix all spelling errors
#48 opened Jan 13, 2025 by IBims1NicerTobi
Add "Unreachable from" info to the "Latency counting couldn't reach this node" error
#36 opened Dec 2, 2024 by VonTum
Verilog / VHDL code sample on hover for "extern" modules documentation Improvements or additions to documentation enhancement New feature or request good first issue Good for newcomers
#35 opened Nov 26, 2024 by VonTum
Default interface should have no name, instead of copying "Constructor convention" enhancement New feature or request good first issue Good for newcomers Request Input These are issues about the design of the language, and thus should be discussed
#34 opened Nov 21, 2024 by VonTum
Explicit latency annotations on Values? enhancement New feature or request Request Input These are issues about the design of the language, and thus should be discussed
#33 opened Nov 21, 2024 by VonTum
On-save regenerating of Verilog/VHDL files enhancement New feature or request good first issue Good for newcomers
#30 opened Nov 13, 2024 by VonTum
@IBims1NicerTobi
Annotations to modules, operators, and declarations that are passed to the generated SV or VHDL code enhancement New feature or request
#29 opened Nov 13, 2024 by VonTum
Ranged Integers enhancement New feature or request
#28 opened Nov 12, 2024 by VonTum
3 of 5 tasks
1
@IBims1NicerTobi
1
Floating-point wrappers in the STL enhancement New feature or request Systementwurf
#27 opened Nov 12, 2024 by VonTum
3 tasks
6
Website enhancement New feature or request Systementwurf
#26 opened Nov 12, 2024 by VonTum
3 tasks
1
Resource usage reporting on hover enhancement New feature or request good first issue Good for newcomers
#24 opened Nov 9, 2024 by VonTum
5 tasks
VHDL Backend enhancement New feature or request good first issue Good for newcomers Systementwurf
#23 opened Nov 9, 2024 by VonTum
@IBims1NicerTobi
6
Submodule Latency Count Inference enhancement New feature or request
#22 opened Nov 9, 2024 by VonTum
6 of 9 tasks
@VonTum
Variadic Template args enhancement New feature or request Request Input These are issues about the design of the language, and thus should be discussed
#21 opened Nov 9, 2024 by VonTum
Distinguish between regular comments and doc-comments documentation Improvements or additions to documentation enhancement New feature or request good first issue Good for newcomers
#20 opened Nov 4, 2024 by VonTum
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