XLS: Accelerated HW Synthesis
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Updated
May 31, 2024 - C++
XLS: Accelerated HW Synthesis
DaCe - Data Centric Parallel Programming
Intermediate Language (IL) for Hardware Accelerator Generators
An open-source hw/sw co-design framework for heterogeneous chips
CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
HeteroCL-MLIR dialect for accelerator design
Allo: A Programming Model for Composable Accelerator Design
The repository contains the coursework in the EE6470 course of NTHU's Electronic System Level Design and Synthesis.
PandA-bambu public repository
Mixing HLS and Backend Versions in Vitis
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis
Time-sensitive affine types for predictable hardware generation
This project is part of the B.Tech degree in Electronics and Telecommunication Engineering at KIIT University.
Implementation of the N^2-formulation of N-body simulation with Vivado HLS for SDAccel platforms.
A formally verified high-level synthesis tool based on CompCert and written in Coq.
Transpiles a subset of Python functions into synthesizable SystemVerilog.
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