Haskell to VHDL/Verilog/SystemVerilog compiler

Hardware Description Languages

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

SystemRDL 2.0 language compiler front-end

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

ACT hardware description language and core tools.

Control and status register code generator toolchain

A place to keep my synthesizable verilog examples.

A core language for rule-based hardware design 🦑

Library code for upcoming RetroClash book

Fearless hardware design

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

🔁 elastic circuit toolchain

Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone compute…

Generator for wokwi schematics that implement lookup tables in conjunctive normal form (CNF), i.e. with AND and OR gates

VHDL Guide

Parser and Lexer to Hardware Description Language using Prolog

A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.