better renaming

info.yaml

@@ -18,7 +18,7 @@ project:
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
     - "project.v"
-    - "tt_um_lfsr_stevej.sv"
+    - "lfsr.sv"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:

src/tt_um_lfsr_stevej.sv → src/lfsr.sv

@@ -1,7 +1,7 @@
 `ifndef _LFSR_
 `define _LFSR_
 
-module tt_um_lfsr_stevej (
+module lfsr (
     input logic clk,
     input logic rst_n,
     input logic write_enable,  // Set the seed

src/project.v

@@ -5,9 +5,9 @@
 
 `default_nettype none
 
-`include "tt_um_lfsr_stevej.sv"
+`include "lfsr.sv"
 
-module tt_um_example (
+module tt_um_lfsr_stevej (
     input  wire [7:0] ui_in,    // Dedicated inputs
     output wire [7:0] uo_out,   // Dedicated outputs
     input  wire [7:0] uio_in,   // IOs: Input path
@@ -24,7 +24,7 @@ module tt_um_example (
   assign uio_oe  = 8'b0000_0000;
 
 
- tt_um_lfsr_stevej lsfr0 (
+ lfsr lsfr0 (
     .clk(clk),
     .rst_n(rst_n),
     .write_enable(uio_in[0]),

test/Makefile

@@ -5,7 +5,7 @@
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = project.v tt_um_lfsr_stevej.sv
+PROJECT_SOURCES = project.v lfsr.sv
 
 ifneq ($(GATES),yes)
 

test/tb.v

@@ -28,7 +28,7 @@ module tb ();
 `endif
 
   // Replace tt_um_example with your module name:
-  tt_um_example user_project (
+  tt_um_lfsr_stevej user_project (
 
       // Include power ports for the Gate Level test:
 `ifdef GL_TEST