add eco system v2 binfile support

[peteasa]

In the simplest use case setting reloadfpga = False in the call to Pyrpl can be used. In this case the user has to ensure that the correct FPGA and device tree is loaded manually.

This commit adds support for the 2.0 ecosystem and in addition allows custom FPGA to be loaded.

To use a custom FPGA the original parameters may still be used:

p = Pyrpl(hostname=HOSTNAME,
    reloadfpga = True, filename = 'red_pitaya.bin')

2.0 ecosystem uses the AMD Xilinx fpga-manager-script fpgautil to configure the device tree (Full) and load the FPGA. In addition the 2.0 ecosystem leaves an audit trail that identifies the FPGA that has been loaded. The file rp-xxxxxx:/tmp/loaded_fpga.inf contains the name of the FPGA loaded.

This change conforms to this protocol and will update loaded_fpga.inf and in addition creates a separate file (rp-xxxxxx:/tmp/update_fpga.txt) with more details about the ecosystem FPGA or the custom FPGA that is in use. The custom FPGA is provided as a parameter to Pyrpl(). The code in this commit then handles the actual FPGA update.

This change is preferable to the pull request 518 because it provides a script "update_fpga.sh" (to be run on the RedPitaya) that allows both the eco system pyrpl or a custom fpga to be loaded whilst conforming to the 2.0 ecosystem protocol. Pull request 518 leaves it up to the user to install the custom fpga and this approach has already generated support issues ( see Modifying FPGA code in Pyrpl ).

In the simple use case mentioned above the FPGA can be loaded automatically at the start of a session and then reloadfpga set to False to prevent it being overwritten later by subsequent calls to Pyrpl(). The separate file rp-xxxxxx:/tmp/update_fpga.txt provides details of the FPGA that can be viewed on the RedPitaya hardware to confirm the details of the FPGA loaded.

Note that the device tree is provided by the v2.0 ecosystem so any custom FPGA must be developed accordingly.

[peteasa]

Note that this commit does not depend upon any other commit. In particular pull request 548 does not depend upon this commit and this pull request does not depend upon [548]. However with a few lines of code change in redpitaya.py the overlay device tree blob generated by pull request 548 can be loaded via new parameters to the Pyrpl() api.

The new file pyrpl/update_fpga.sh that runs on the RedPitaya board, introduced by this commit, is actually more generic and could be used by anyone trying to load any custom project (pyrpl, logic, axi4lite, stream_app, classic ...). The script is needed to ensure that the remaining RedPitaya tools and applications know that a custom FPGA has been loaded.

[michaelcroquette]

This looks good ! I just want to fully test it and I just have IP address issues with the 2.0 ecosystem. I preferred the old way to set a static IP address but I'll get over it.

[peteasa]

I think that I should add the devicetree load as well as the fpga load

[peteasa]

Note that my solution should work with both the OS2 system and the older system from https://sourceforge.net/projects/pyrpl/files/

My code detects that you are using an older RedPitaya OS and behaves in a legacy way.. #547 has been designed explicitly to support the older and the new OS.. backward compatible and all that!

If it does not work let me know the exact reason why it fails and lets fix it!

[michaelcroquette]

Hello,
So I'm finally able to work again on pyrpl. i have an issue with the OS 2.0 where I can't open an ssh connection to the RP. I had to modified the RP IP address and set it to static because I'm not working with a DHCP so that might be the issue but I'm surprised because if I enter the IP address in a browser I can access the 'My Red Pitaya" page. Did you had any similar issue ? I preferred when the IP address was just written on a config file on the SD card.

[peteasa]

The trick with SSH problems is to run ssh -vvv root@rp-f0bd75
In my case I found that since I have multiple machines that I log into ssh got confused. I have already pushed that change to pyrpl-fpga and RedPitaya version of pyrpl but here is the original pull request - peteasa@fc2b44c

The UPnP problem that you have could be related to getting the IP address or something else.. exactly what is the error message?