Derivative term in the PID

[Bentwin2002]

Do you know why the D term in the PID was deactivated? Has anyone had any success reactivating and using the D term?

[michaelcroquette]

The D term was unused in our experiments most of the time so we removed it. It is active in the default RedPitaya PID module if you really need it.

[mixgreen]

The D term was unused in our experiments most of the time so we removed it. It is active in the default RedPitaya PID module if you really need it.

Is that mean i can't use the D term in pyrpl? if i really need it , is that posiable to uncomment the code to use it?

[michaelcroquette]

Actually you can ! I thought the derivative had been disabled in fpga code but it was actually uncommented in #22. There is a comment in the code saying "Derivative - 2 cycles delay (but treat as 1 cycle because its not functional at the moment" but I'm not sure what it means.
The python code of the PID module was commented in #299 but there is no mention of this modification in the commit description.
Anyway you can try and see ! It looks like the fpga code is the same as the original one from redpitaya so I think it should work. If it works we will uncomment it.

[nicoleroy-ipgp]

Hi, I am also trying to use the derivative term of the PID module. I uncommented all the python code related to it but it seems that it is deactivated in the FPGA code here : pyrpl/fpga/rtl/red_pitaya_pid_block.v, with those lines :
70 parameter DERIVATIVE = 0 , //disables differential gain if 0
273 if (DERIVATIVE == 1) begin

I am new to Red Pitaya and PyRPL (and FPGA too ...). What is the best way to reactivate this derivative term in your opinion ?
I tried to recompile the FPGA code but I am struggling with Vivado versions under Linux (need to pass some scripts by Vivado 2015.4 but current version is 2024.2 ...)

Any advice would be appreciated !!
Thanks

[michaelcroquette]

Hello Nicolas,

I will create a branch on the git with the derivative active and without the IIR module (I think the reason Leo removed the derivative term was to gain computation power to fit the (big) IIR module on the FPGA). If you already have a branch you can publish it and send it and I will compile it.

[nicoleroy-ipgp]

Hello Michael,
Thanks a lot !
I managed to recompile the FPGA code with DERIVATIVE = 1 (using Vivado 2015.4) but it does not seem to work. The available range of "d" parameter is quite small (but it might be normal) and nothing changes when I modify it. I am not sure that the code has been downloaded to the Red Pitaya (I put it in /opt/pyrpl with the right name following red_pitaya.py code).
I also tried to use this branch : https://github.com/RedPitaya/pyrpl/tree/with_differentiator_piD but this does not work (it seems quite old ...)
And no, I have no branch.
Thanks for your help !

[michaelcroquette]

So I guess you have your local copy of the code you modified and compile ? There's no need to "put" the code anywhere else than where it was before. What is the folder /opt/pyrpl ?

You can comment the IIR module generation part to check if you are actually using the proper code (check c129569).

[nicoleroy-ipgp]

Yes I modified both the python and FPGA codes locally to try a few modifications (I don't fully understand the whole code yet ...). Then I compiled the FPGA code and put the generated red_pitaya.bin file in the directory /opt/pyrpl with name fpga.bin whichare the defaultparameters in file redpitaya.py (I understood that this file is copied when pyrpl is started depending on the options in redpitaya.py). Otherwise I don't understand how the modified FPGA firmware is uploaded to the FPGA. But I am fairly new to Red Pitaya and FPGA so my understanding of the whole process is limited ...
Thanks for your help !

[nicoleroy-ipgp]

I did a few tests and I have the confirmation that my FPGA code is not uploaded to the Red Pitaya. So I guess that I am missing something in the whole process ...
Once the file red_pitaya.bin is generated, is there anything to do to upload it to the device ?
Thanks !

[nicoleroy-ipgp]

I am using the latest Pitaya OS, that might be the issue because it is not the same way to upload the .bin file to the FPGA, now it uses fpgautil. But I get an error when trying to reprogram the FPGA with my code and fpgautil ...

[michaelcroquette]

This could be the issue. If you look at the last Pull requests there are some suggestions to resolve compatibility issues with the new RedPitaya OS. I'm lacking time for now to review those PRs and to try and solve your issue.
Good luck !

[michaelcroquette]

I created this [branch] (https://github.com/pyrpl-fpga/pyrpl/tree/derivative_on_PID) where I've modified the FPGA code so the derivative is active. There still seems to be saturation issues but you can already test it if you want.

[nicoleroy-ipgp]

Thanks a lot ! I managed to compile the FPGA code but I am still unable to upload it to the FPGA. I tried OS 0.94 and OS2.00-37 with no luck ... I get the following error :
sh: 1: echo: echo: I/O error
BIN FILE loading through FPGA manager failed

I tried to generated the bin file using bootgen etc... but nothing seems to work.

Could you share what version of Red Pitaya OS you are using for your tests, please ?

Thanks a lot for your help !

[michaelcroquette]

I'm using this OS. Once you've compiled there is nothing to do apart from restarting pyrpl with reload_fpga=True and it will load the new generated bitfile. But yes the loading of the bitfile is different on the new OS, you can try Pete's solution if you want to work with a newer OS but I haven't tested it.

[nicoleroy-ipgp]

I am using the low noise version of Red Pitaya 125-14 with a Z7020. I understand that there might be a difference with Z7010 for compilation. That might be the cause of my issues ...
Thanks for your links, I will try this tomorrow.