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Fix for issue #58 #85

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Fix for issue #58 #85

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1e79901
Fix for issue #58
Silabs-ArjanB Oct 8, 2020
49c2c8f
merge from master
Silabs-ArjanB Oct 27, 2020
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3 changes: 1 addition & 2 deletions src/dm_csrs.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -510,7 +510,7 @@ module dm_csrs #(
if (dmcontrol_q.resumereq && resumeack_i) begin
dmcontrol_d.resumereq = 1'b0;
end
// static values for dcsr
// static values for sbcs
sbcs_d.sbversion = 3'b1;
sbcs_d.sbbusy = sbbusy_i;
sbcs_d.sbasize = $bits(sbcs_d.sbasize)'(BusWidth);
Expand All @@ -519,7 +519,6 @@ module dm_csrs #(
sbcs_d.sbaccess32 = logic'(BusWidth == 32'd32);
sbcs_d.sbaccess16 = 1'b0;
sbcs_d.sbaccess8 = 1'b0;
sbcs_d.sbaccess = (BusWidth == 32'd64) ? 3'd3 : 3'd2;
end

// output multiplexer
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27 changes: 20 additions & 7 deletions src/dm_sba.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -101,7 +101,7 @@ module dm_sba #(
unique case (state_q)
dm::Idle: begin
// debugger requested a read
if (sbaddress_write_valid_i && sbreadonaddr_i) state_d = dm::Read;
if (sbaddress_write_valid_i && sbreadonaddr_i) state_d = dm::Read;
// debugger requested a write
if (sbdata_write_valid_i) state_d = dm::Write;
// perform another read
Expand Down Expand Up @@ -140,12 +140,25 @@ module dm_sba #(
default: state_d = dm::Idle; // catch parasitic state
endcase

// handle error case
if (sbaccess_i > 3 && state_q != dm::Idle) begin
req = 1'b0;
state_d = dm::Idle;
sberror_valid_o = 1'b1;
sberror_o = 3'd3;
// check for SBA configuration errors at start of transaction
if (state_q != dm::Idle) begin
// handle unsupported sbaccess value error case (currently only supporting full bus width transfers)
if (!(((sbaccess_i == 3'd2) && (BusWidth == 32'd32)) || ((sbaccess_i == 3'd3) && (BusWidth == 32'd64)))) begin
req = 1'b0;
state_d = dm::Idle;
sberror_valid_o = 1'b1;
sberror_o = 3'd4;
end else begin
// handle misalignment case
if (((sbaccess_i == 3'd1) && (sbaddress_i[0:0] != 1'b0)) ||
((sbaccess_i == 3'd2) && (sbaddress_i[1:0] != 2'b0)) ||
((sbaccess_i == 3'd3) && (sbaddress_i[2:0] != 3'b0))) begin
req = 1'b0;
state_d = dm::Idle;
sberror_valid_o = 1'b1;
sberror_o = 3'd3;
end
end
end
// further error handling should go here ...
end
Expand Down