Fix for OpenSTA issue 398 and OpenROAD issue 9454 with regression#401
Fix for OpenSTA issue 398 and OpenROAD issue 9454 with regression#401parallaxsw merged 5 commits intoparallaxsw:masterfrom
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Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
| verilog_specify | ||
| verilog_write_escape | ||
| verilog_unconnected_dbterm | ||
| } |
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dbterm is ODB terminolgy, which is irrelevant here. use unconnected_hpin
test/verilog_unconnected_dbterm.tcl
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| @@ -0,0 +1,14 @@ | |||
| read_liberty ../examples/nangate45_typ.lib.gz | |||
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asap7_small.lib is a smaller library to use for simple tests
test/verilog_unconnected_dbterm.tcl
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| } else { | ||
| puts "b2/u3/Z is not connected to any net." | ||
| } | ||
| puts "Find internal net connected to b2/out2: [get_property [get_net b2/out2] full_name]" No newline at end of file |
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use get_full name like above instead of get_property
but both are overkill. easier to just use report_net to see the pin listed than all of this
printing/if logic
verilog/VerilogReader.cc
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| // Ensure pin exists (may have been pre-created), then connect to parent | ||
| // net if present. Always create a term for the child-side net. | ||
| Pin *pin = network_->findPin(inst, port); | ||
| if (pin == nullptr) |
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This cannot happen now that all of the pins are already made.
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
verilog/VerilogReader.cc
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| } | ||
| // Make all pins so timing arcs are built and get_pins finds them. | ||
| ConcreteCellPortBitIterator port_iter(reinterpret_cast<const ConcreteCell*>(cell)); | ||
| while (port_iter.hasNext()) { |
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I think this would be better off using Network::portBitIterator so there are no casts involved.
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Network::portBitIterator returns a heap-allocated CellPortBitIterator*, So I will have to use a delete on it later, would that be okay? (this is the pattern used in ConcreteNetwork::makePins)
Otherwise I can also use std::unique_ptr port_iter(network_->portBitIterator(cell))
Please let me know your preference. Thanks
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yes, you have to delete it either explicitly (like all the other network iterator calls you can find in OpenSTA) or use unique_ptr which I haven't adopted much because it makes the declaration lines sooooo wiiiiddddde.
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Gotcha! Done.
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
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Did you resolve the openroad issues you mentioned in the issue? |
Yes- But only after I pulled all the OpenSTA changes into OpenROAD (that also needed some OpenROAD changes due to the string vector changes in StringUtil). After that OpenROAD issue w.r.t. this issue was resolved. |
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Issue: #398
Instance b2 is of the type block2 which has a 2nd output pin "out2". Even if it is unconnected to any net in the top level (i.e. the "top" module), the pin b2/out2 should be still a valid object.
Potential fix per feedback in the issue.
So in
VerilogReader::makeModuleInstNetworkI just enhanced the existing code that was for liberty cells only to include non-liberty cells tooNeeded an updation in
VerilogReader::makeInstPinbecause we have already called makePin now even for non-liberty cells by the new change- so need to make sure we don't create duplicate here.Added a regression for the issue.