Fix for OpenSTA issue 398 and OpenROAD issue 9454 with regression (#401)

* Fix for OpenSTA issue 398 and OpenROAD issue 9454 with regression

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* Incorporated feedbacks from previous version

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* rename tests

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* remove unnecessary newline

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* Updated to use network_->portBitIterator

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

---------

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

Author: dsengupta0628

test/regression_vars.tcl

@@ -166,6 +166,7 @@ record_public_tests {
   verilog_attribute
   verilog_specify
   verilog_write_escape
+  verilog_unconnected_hpin
 }
 
 define_test_group fast [group_tests all]

test/verilog_unconnected_hpin.ok

@@ -0,0 +1,13 @@
+Find b1/out2: b1/out2
+Find b2/out2: b2/out2
+Net b2/out2
+ Pin capacitance: 0.00
+ Wire capacitance: 0.00
+ Total capacitance: 0.00
+ Number of drivers: 1
+ Number of loads: 0
+ Number of pins: 1
+
+Driver pins
+ b2/u3/Y output (BUFx2_ASAP7_75t_R)
+

test/verilog_unconnected_hpin.tcl

@@ -0,0 +1,9 @@
+read_liberty asap7_small.lib.gz
+read_verilog verilog_unconnected_hpin.v
+link_design top 
+puts "Find b1/out2: [get_full_name [get_pins b1/out2]]"
+puts "Find b2/out2: [get_full_name [get_pins b2/out2]]"
+# Check if net is connected to "b2/u3/Y" that was the b2/out2 in parent block
+set iterm [sta::find_pin "b2/u3/Y"]
+set net [get_net -of_object [get_pin $iterm]]
+report_net [get_full_name $net]

test/verilog_unconnected_hpin.v

@@ -0,0 +1,24 @@
+module top (in, clk1, clk2, out, out2);
+   input in, clk1, clk2;
+   output out, out2;
+   block1 b1 (.in(in), .clk(clk1), .out(b1out), .out2(out2));
+   block2 b2 (.in(b1out), .clk(clk2), .out(out));
+endmodule // top
+
+module block1 (in, clk, out, out2);
+   input in, clk;
+   output out, out2;
+   BUFx2_ASAP7_75t_R u1 (.A(in), .Y(u1out));
+   DFFHQx4_ASAP7_75t_R  r1 (.D(u1out), .CLK(clk), .Q(r1q));
+   BUFx2_ASAP7_75t_R u2 (.A(r1q), .Y(out));
+   BUFx2_ASAP7_75t_R u3 (.A(out), .Y(out2));
+endmodule // block1
+
+module block2 (in, clk, out, out2);
+   input in, clk;
+   output out, out2;
+   BUFx2_ASAP7_75t_R u1 (.A(in), .Y(u1out));
+   DFFHQx4_ASAP7_75t_R  r1 (.D(u1out), .CLK(clk), .Q(r1q));
+   BUFx2_ASAP7_75t_R u2 (.A(r1q), .Y(out));
+   BUFx2_ASAP7_75t_R u3 (.A(out), .Y(out2));
+endmodule // block2

verilog/VerilogReader.cc

@@ -1824,14 +1824,13 @@ VerilogReader::makeModuleInstNetwork(VerilogModuleInst *mod_inst,
       }
     }
 
-    if (lib_cell) {
-      // Make all pins so timing arcs are built.
-      LibertyCellPortBitIterator port_iter(lib_cell);
-      while (port_iter.hasNext()) {
-        LibertyPort *port = port_iter.next();
-        network_->makePin(inst, reinterpret_cast<Port*>(port), nullptr);
-      }
+    // Make all pins so timing arcs are built and get_pins finds them.
+    CellPortBitIterator *port_iter = network_->portBitIterator(cell);
+    while (port_iter->hasNext()) {
+      Port *port = port_iter->next();
+      network_->makePin(inst, port, nullptr);
     }
+    delete port_iter;
     bool is_leaf = network_->isLeaf(cell);
     VerilogBindingTbl bindings(zero_net_name_, one_net_name_);
     if (mod_inst->hasPins()) {
@@ -1983,8 +1982,11 @@ VerilogReader::makeInstPin(Instance *inst,
       network_->connect(inst, port, net);
   }
   else {
-    Pin *pin = network_->makePin(inst, port, net);
-    if (!is_leaf && net) {
+    // Pin should already exist by prior makePin, then connect to parent
+    // net if present and create a term for the child-side net.
+    Pin *pin = network_->findPin(inst, port);
+    if (net) {
+      network_->connect(inst, port, net);
       const char *port_name = network_->name(port);
       Net *child_net = bindings->ensureNetBinding(port_name, inst, network_);
       network_->makeTerm(pin, child_net);