Repositories list

• oss-cad-suite-build

  Public

  YosysHQ/oss-cad-suite-build’s past year of commit activity
  Multi-platform nightly builds of open source digital design and verification tools

  Shell

  •

  ISC License

  •108•1.3k•73•7•Updated Jan 8, 2026Jan 8, 2026

• yosys

  Public

  YosysHQ/yosys’s past year of commit activity
  Yosys Open SYnthesis Suite

  C++

  •

  ISC License

  •1k•4.2k•490•108•Updated Jan 8, 2026Jan 8, 2026

• apicula

  Public

  YosysHQ/apicula’s past year of commit activity
  Project Apicula 🐝: bitstream documentation for Gowin FPGAs

  Verilog

  •

  MIT License

  •83•615•20•3•Updated Jan 7, 2026Jan 7, 2026

• sby

  Public

  YosysHQ/sby’s past year of commit activity
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

  Python

  •

  Other

  •87•485•42•10•Updated Jan 7, 2026Jan 7, 2026

• riscv-formal

  Public

  YosysHQ/riscv-formal’s past year of commit activity
  RISC-V Formal Verification Framework

  Verilog

  •

  ISC License

  •39•174•7•3•Updated Jan 6, 2026Jan 6, 2026

• abc

  Public

  YosysHQ/abc’s past year of commit activity
  ABC: System for Sequential Logic Synthesis and Formal Verification

  C

  •

  Other

  •719•30•0•2•Updated Jan 5, 2026Jan 5, 2026

• nextpnr

  Public

  YosysHQ/nextpnr’s past year of commit activity
  nextpnr portable FPGA place and route tool

  C++

  •

  ISC License

  •279•1.6k•111•12•Updated Jan 5, 2026Jan 5, 2026

• prjpeppercorn

  Public

  YosysHQ/prjpeppercorn’s past year of commit activity
  Project Peppercorn - GateMate FPGA Bitstream Documentation

  Python

  •

  ISC License

  •3•31•0•1•Updated Dec 30, 2025Dec 30, 2025

• prjpeppercorn-test-cases

  Public

  YosysHQ/prjpeppercorn-test-cases’s past year of commit activity
  Project Peppercorn GateMate Test Cases

  Verilog

  •

  ISC License

  •6•11•0•0•Updated Dec 26, 2025Dec 26, 2025

• mcy

  Public

  YosysHQ/mcy’s past year of commit activity
  Mutation Cover with Yosys (MCY)

  C++

  •

  ISC License

  •14•89•1•1•Updated Dec 3, 2025Dec 3, 2025

• eqy

  Public

  YosysHQ/eqy’s past year of commit activity
  Equivalence checking with Yosys

  C++

  •

  Other

  •9•54•22•0•Updated Dec 3, 2025Dec 3, 2025

• prjtrellis

  Public

  YosysHQ/prjtrellis’s past year of commit activity
  Documenting the Lattice ECP5 bit-stream format.

  Python

  •

  Other

  •96•436•37•14•Updated Oct 27, 2025Oct 27, 2025

• sby-gui

  Public

  YosysHQ/sby-gui’s past year of commit activity
  GUI for SymbiYosys

  C++

  •

  ISC License

  •5•17•7•1•Updated Oct 13, 2025Oct 13, 2025

• nerv

  Public
  Naive Educational RISC V processor

  SystemVerilog

  •

  Other

  •17•94•2•1•Updated Oct 12, 2025Oct 12, 2025

• icestorm

  Public
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

  Python

  •

  ISC License

  •235•1.1k•47•20•Updated Sep 22, 2025Sep 22, 2025

• prjtrellis-db

  Public
  Project Trellis database

  Creative Commons Zero v1.0 Universal

  •12•14•0•1•Updated Sep 15, 2025Sep 15, 2025

• scy

  Public

  YosysHQ/scy’s past year of commit activity
  Sequence of Covers with Yosys

  SystemVerilog

  •

  Other

  •1•6•1•0•Updated Sep 4, 2025Sep 4, 2025

• rtlil-mlir

  Public
  Yosys RTLIL dialect for MLIR

  C++

  •

  ISC License

  •1•13•1•0•Updated Jun 12, 2025Jun 12, 2025

• furo-ys

  Public
  A clean customizable documentation theme for Sphinx

  Sass

  •

  MIT License

  •369•1•0•0•Updated Apr 21, 2025Apr 21, 2025

• mau

  Public

  YosysHQ/mau’s past year of commit activity
  Modular Application Utilities

  Python

  •

  ISC License

  •3•5•1•0•Updated Feb 12, 2025Feb 12, 2025

• imctk

  Public
  Incremental Model Checking Toolkit

  Rust

  •

  Other

  •2•10•41•1•Updated Jan 30, 2025Jan 30, 2025

• nextpnr-tests

  Public
  Verilog

  •

  ISC License

  •5•6•2•2•Updated Jan 16, 2025Jan 16, 2025

• yosyshq.github.io

  Public

  YosysHQ/yosyshq.github.io’s past year of commit activity
  www.yosyshq.net

  HTML

  •1•4•0•0•Updated Oct 7, 2024Oct 7, 2024

• yosys-web

  Public
  Yosys Web Page

  HTML

  •6•2•1•0•Updated Oct 7, 2024Oct 7, 2024

• picorv32

  Public

  YosysHQ/picorv32’s past year of commit activity
  PicoRV32 - A Size-Optimized RISC-V CPU

  Verilog

  •

  ISC License

  •888•3.9k•67•15•Updated Jun 27, 2024Jun 27, 2024

• VlogHammer

  Public
  A Verilog Synthesis Regression Test

  Shell

  •12•37•0•3•Updated Mar 21, 2024Mar 21, 2024

• setup-oss-cad-suite

  Public
  Set up your GitHub Actions workflow with a OSS CAD Suite

  TypeScript

  •

  ISC License

  •3•16•4•1•Updated Mar 21, 2024Mar 21, 2024

• padring

  Public
  A padring generator for ASICs

  asicedachip+ 2vlsiyosys

  C++

  •

  ISC License

  •12•25•2•1•Updated May 17, 2023May 17, 2023

• .github

  Public

  YosysHQ/.github’s past year of commit activity
  0•0•0•0•Updated Apr 4, 2023Apr 4, 2023

• yosys-manual-build

  Public archive
  Yosys manual

  Dockerfile

  •0•1•0•0•Updated Oct 24, 2022Oct 24, 2022