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Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
#5564
opened Dec 22, 2025 by
rocallahan
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Defer redirecting cell outputs when merging cells in
opt_merge untill after we've done a full pass over the cells.
#5555
opened Dec 19, 2025 by
rocallahan
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abc: add -word mode which uses word-level cells where possible
#5554
opened Dec 18, 2025 by
nataliakokoromyti
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docs: shuffle and expand contributing info
documentation
#5531
opened Dec 3, 2025 by
widlarizer
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Draft
Makefile: install frontends/verilog/verilog_location.h.
discuss
needs further discussion on the YosysHQ discourse (https://yosyshq.discourse.group)
#5529
opened Dec 2, 2025 by
Muxianesty
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Document and regression-test staged/cosimulation-based verification
#5528
opened Dec 2, 2025 by
gussmith23
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Draft
1 task
.github: trigger everything that triggers on main or PRs on merge queue
#5521
opened Nov 27, 2025 by
widlarizer
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celltypes: compile-time lookup tables for internal cells
#5512
opened Nov 25, 2025 by
widlarizer
•
Draft
1 task
proc_mux: use assignment action locations for mux src
#5456
opened Nov 2, 2025 by
widlarizer
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2 of 3 tasks
gowin: dsp: Add basic DSP block inferencing for various MULT cells
#5411
opened Oct 7, 2025 by
plaes
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Unify handling of quoted strings in pass args
#5385
opened Sep 24, 2025 by
KrystalDelusion
•
Draft
4 tasks done
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