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SystemVerilog interface signals being omitted during synthesis

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5567 In YosysHQ/yosys;

· Cpt-Quantum opened on Dec 22, 2025

FSM synth unexpected results

Status: Open.

#5558 In YosysHQ/yosys;

· ulmitov opened on Dec 19, 2025

Behavior of <code>Module::connect()</code> with constants is confusing

Status: Open.

#5556 In YosysHQ/yosys;

· rocallahan opened on Dec 19, 2025

Let opt_dff combine flops with arbitrary forms of equivalent logic

feature-request

Status: Open.

Feature

#5551 In YosysHQ/yosys;

· widlarizer opened on Dec 17, 2025

Yosys aborts with exception in simulation pass

documentation

error-handlingError handling and reportingError handling and reporting

Status: Open.

#5534 In YosysHQ/yosys;

· qinkejiu opened on Dec 5, 2025

read_verilog doesn't support imports in packages

feature-request

SystemVerilogIssues and questions related to SystemVerilogIssues and questions related to SystemVerilog

Status: Open.

#5533 In YosysHQ/yosys;

· the-moog opened on Dec 3, 2025

Unify info about make test and make unit-test

documentation

Status: Open.

#5523 In YosysHQ/yosys;

· widlarizer opened on Nov 28, 2025

Unify make test and make unit-test

feature-request

Status: Open.

#5522 In YosysHQ/yosys;

· widlarizer opened on Nov 28, 2025

Less wasteful CellTypes usage in opt_clean

feature-request

Status: Open.

#5509 In YosysHQ/yosys;

· widlarizer opened on Nov 25, 2025

<code>yosys-smtbmc</code> cannot load Yosys witness when design differs slightly; error message unhelpful

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5503 In YosysHQ/yosys;

· gussmith23 opened on Nov 24, 2025

<code>proc_prune</code> undefines connections / incorrect scheduling semantics optimisation

pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction

Status: Open.

#5487 In YosysHQ/yosys;

· toby-bro opened on Nov 14, 2025

cxxrtl: timing bug in flip-flop evaluation

bug

cxxrtl

Status: Open.

#5471 In YosysHQ/yosys;

· toby-bro opened on Nov 6, 2025