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CLAP v0.1.1.0-alpha
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@u8cat u8cat released this 12 Aug 18:06
· 26 commits to main since this release
v0.1.1.0-alpha
16b80a7

Dhrystone

total clock             is 211031
total instruction       is 62048
instruction per cycle   is 0.294023
simulation time         is 4.635560 s

Coremark

total clock             is 483633
total instruction       is 375026
instruction per cycle   is 0.775435
simulation time         is 15.171792 s

Implementation Default (100MHz)

WNS: -2.096ns, TNS: -3596.510, TNS Failing Endpoints: 7416, LUT: 49118, FF: 31670, BRAM: 33.5, DSP: 4

Estimated clock frequency: 82.67MHz

Assets 4
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