Releases: npz7yyk/clap
Releases · npz7yyk/clap
CLAP v0.2.0.0-beta
Clock Frequency
80.8MHz
Performance
| Benchmarks | Reference | Run Time | Ratio |
|---|---|---|---|
| A0_1-limits01 | 43.5077 | 8.59177 | 5.06388 |
| A1_1-large03 | 62.2865 | 29.5317 | 2.10914 |
| B0_10-test19 | 508.288 | 93.0654 | 5.46162 |
| B2_50-test19 | 333.118 | 82.8083 | 4.02276 |
| B3_50-test19 | 279.832 | 83.2205 | 3.36254 |
| B5_500-test19 | 554.867 | 156.22 | 3.55183 |
| D0_100-test07 | 286.818 | 95.9582 | 2.98899 |
| D0_1000-test10 | 553.577 | 246.948 | 2.24167 |
| D0_1000-test06 | 119.142 | 123.142 | 0.967517 |
| F0_1-test8 | 47.4547 | 11.4117 | 4.15843 |
| G0_10-test03 | 898.276 | 187.288 | 4.79623 |
| G0_10-test06 | 587.155 | 136.769 | 4.29304 |
| H0_40-test03 | 349.407 | 84.2216 | 4.14866 |
| I2_10-test1 | 167.637 | 26.3194 | 6.36932 |
| coremark-0 | 177.385 | 21.3837 | 8.29535 |
| coremark-1 | 177.932 | 21.4363 | 8.30049 |
| dhrystone-5000000 | 197.368 | 197.368 | 4.9836 |
| geomean | 3.95387 |
CLAP v0.1.1.0-alpha
Dhrystone
total clock is 211031
total instruction is 62048
instruction per cycle is 0.294023
simulation time is 4.635560 s
Coremark
total clock is 483633
total instruction is 375026
instruction per cycle is 0.775435
simulation time is 15.171792 s
Implementation Default (100MHz)
WNS: -2.096ns, TNS: -3596.510, TNS Failing Endpoints: 7416, LUT: 49118, FF: 31670, BRAM: 33.5, DSP: 4
Estimated clock frequency: 82.67MHz
CLAP v0.1.0.0-alpha
Dhrystone
total clock is 229181
total instruction is 62048
instruction per cycle is 0.270738
simulation time is 3.970445 s
Coremark
total clock is 604933
total instruction is 374753
instruction per cycle is 0.619495
simulation time is 13.042218 s
Implementation Default (100MHz)
WNS: -1.615ns, TNS: -1857.671ns, TNS Failing Endpoints: 4853, LUT: 47573, FF: 30657, BRAM: 33.5, DSP: 4
Estimated clock frequency: 86.09MHz
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) : -1.615ns (required time - arrival time)
Source: cpu_mid/the_exe/eu0_rd_0_reg[4]/C
(rising edge-triggered cell FDRE clocked by clk_out1_clk_pll_33 {[email protected] [email protected] period=10.000ns})
Destination: cpu_mid/the_dcache/req_buf/dout_reg[5]/D
(rising edge-triggered cell FDRE clocked by clk_out1_clk_pll_33 {[email protected] [email protected] period=10.000ns})
Path Group: clk_out1_clk_pll_33
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_out1_clk_pll_33 [email protected] - clk_out1_clk_pll_33 [email protected])
Data Path Delay: 11.421ns (logic 3.611ns (31.618%) route 7.810ns (68.382%))
Logic Levels: 19 (CARRY4=6 LUT2=1 LUT3=1 LUT4=5 LUT5=1 LUT6=5)
Clock Path Skew: -0.223ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 7.603ns = ( 17.603 - 10.000 )
Source Clock Delay (SCD): 8.337ns
Clock Pessimism Removal (CPR): 0.511ns
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.136ns
Phase Error (PE): 0.000ns
Slack (VIOLATED) : -1.431ns (required time - arrival time)
Source: cpu_mid/the_exe/eu0_rd_0_reg[4]/C
(rising edge-triggered cell FDRE clocked by clk_out1_clk_pll_33 {[email protected] [email protected] period=10.000ns})
Destination: cpu_mid/the_tlb/output_s1_buffer/dout_reg[56]/D
(rising edge-triggered cell FDRE clocked by clk_out1_clk_pll_33 {[email protected] [email protected] period=10.000ns})
Path Group: clk_out1_clk_pll_33
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_out1_clk_pll_33 [email protected] - clk_out1_clk_pll_33 [email protected])
Data Path Delay: 11.169ns (logic 3.460ns (30.979%) route 7.709ns (69.021%))
Logic Levels: 19 (CARRY4=8 LUT2=1 LUT3=1 LUT4=4 LUT5=1 LUT6=4)
Clock Path Skew: -0.215ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 7.611ns = ( 17.611 - 10.000 )
Source Clock Delay (SCD): 8.337ns
Clock Pessimism Removal (CPR): 0.511ns
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.136ns
Phase Error (PE): 0.000ns
Slack (VIOLATED) : -1.242ns (required time - arrival time)
Source: cpu_mid/the_exe/eu0_rd_0_reg[4]/C
(rising edge-triggered cell FDRE clocked by clk_out1_clk_pll_33 {[email protected] [email protected] period=10.000ns})
Destination: cpu_mid/the_tlb/output_s1_buffer/dout_reg[61]/D
(rising edge-triggered cell FDRE clocked by clk_out1_clk_pll_33 {[email protected] [email protected] period=10.000ns})
Path Group: clk_out1_clk_pll_33
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (clk_out1_clk_pll_33 [email protected] - clk_out1_clk_pll_33 [email protected])
Data Path Delay: 10.983ns (logic 3.460ns (31.504%) route 7.523ns (68.496%))
Logic Levels: 19 (CARRY4=8 LUT2=1 LUT3=1 LUT4=4 LUT5=1 LUT6=4)
Clock Path Skew: -0.213ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 7.613ns = ( 17.613 - 10.000 )
Source Clock Delay (SCD): 8.337ns
Clock Pessimism Removal (CPR): 0.511ns
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.136ns
Phase Error (PE): 0.000ns