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ip_cores/infra-cores: update submodule reference
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@lerwys
lerwys committed Mar 14, 2019
1 parent e0a2f39 commit c5ee2a4
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion hdl/ip_cores/infra-cores
Submodule infra-cores updated 21 files
+4 −0 modules/generic/ifc_generic_pkg.vhd
+7 −4 modules/wishbone/wb_acq_core/acq_core_pkg.vhd
+11 −2 modules/wishbone/wb_acq_core/acq_fsm.vhd
+2 −1 modules/wishbone/wb_acq_core/wb_acq_core.vhd
+0 −1 modules/wishbone/wb_fmcpico1m_4ch/cdc_fifo.vhd
+1 −1 modules/wishbone/wb_pcie_cntr/wb_bpm_pcie.vhd
+1 −1 platform/xilinx/artix7/afc_v3/axi_datamover_0/Manifest.py
+1 −1 platform/xilinx/artix7/afc_v3/axi_datamover_bpm/Manifest.py
+1 −2 platform/xilinx/artix7/afc_v3/axi_interconnect/Manifest.py
+1 −2 platform/xilinx/artix7/afc_v3/axi_interconnect_bpm/Manifest.py
+1 −1 platform/xilinx/artix7/afc_v3/ddr_core/ddr_core.xci
+1 −1 platform/xilinx/artix7/afc_v3/pcie_core/Manifest.py
+9 −9 testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/Manifest.py
+3 −3 testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/defines.v
+66 −0 testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/glbl.v
+232 −214 testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/questa_compile.sh
+7 −7 testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/questa_remove_libs.sh
+5 −5 testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/run.do
+1,807 −1,077 testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wave.do
+0 −1,613 testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wave_compl.do
+92 −27 testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wb_acq_core_tb.v

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