Merge branch 'devel'

lnls-dig · Oct 3, 2018 · e0a2f39 · e0a2f39
2 parents 63d91b5 + 349c211
commit e0a2f39
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Showing 3 changed files with 25 additions and 3 deletions.
diff --git a/.gitignore b/.gitignore
@@ -35,4 +35,13 @@ work/
 *.xpr
 *.edif
 *.mif
-.Xil/
+.Xil/
+
+######################
+# Impact files
+######################
+
+*impact.xsl
+*impact_impact.xwbt
+*usage_statistics_webtalk.html
+*webtalk_impact.xml
diff --git a/hdl/ip_cores/dsp-cores b/hdl/ip_cores/dsp-cores
diff --git a/hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd b/hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd
@@ -706,8 +706,9 @@ architecture rtl of dbe_bpm_gen is
   constant c_acq_monit_amp_id               : natural := 16;
   constant c_acq_monit_pos_id               : natural := 17;
   constant c_trigger_sw_clk_id              : natural := 18;
+  constant c_phase_sync_trigger_id          : natural := 19;
 
-  constant c_trig_num_channels              : natural := 1;
+  constant c_trig_num_channels              : natural := 2;
   -- Number of channels per acquisition core
   constant c_acq_num_channels               : natural := 18; -- ADC + ADC SWAP + MIXER + TBT AMP + TBT POS +
                                                             -- FOFB AMP + FOFB POS + MONIT AMP + MONIT POS + MONIT1 AMP +
@@ -2995,6 +2996,12 @@ begin
     -----------------------------
     rffe_swclk_o                            => dsp1_clk_rffe_swap,
 
+    -----------------------------
+    -- Synchronization trigger for RFFE swap clock
+    -----------------------------
+
+    sync_trig_i                             => trig_pulse_rcv(c_trig_mux_0_id, c_phase_sync_trigger_id).pulse,
+
     -----------------------------
     -- Debug signals
     -----------------------------
@@ -3213,6 +3220,12 @@ begin
     -----------------------------
     rffe_swclk_o                            => dsp2_clk_rffe_swap,
 
+    -----------------------------
+    -- Synchronization trigger for RFFE swap clock
+    -----------------------------
+
+    sync_trig_i                             => trig_pulse_rcv(c_trig_mux_1_id, c_phase_sync_trigger_id).pulse,
+
     -----------------------------
     -- Debug signals
     -----------------------------
+25 −2		hdl/modules/dsp_cores_pkg.vhd
+5 −5		hdl/modules/machine/sirius_bo_250M/machine_pkg.vhd
+5 −5		hdl/modules/machine/sirius_sr_250M/machine_pkg.vhd
+5 −0		hdl/modules/wb_bpm_swap/bpm_swap/bpm_swap.vhd
+3 −1		hdl/modules/wb_bpm_swap/bpm_swap/swap_freqgen.vhd
+6 −1		hdl/modules/wb_bpm_swap/wb_bpm_swap.vhd
+5 −2		hdl/modules/wb_bpm_swap/xwb_bpm_swap.vhd
+8 −1		hdl/modules/wb_position_calc/wb_position_calc_core.vhd
+12 −0		hdl/modules/wb_position_calc/xwb_position_calc_core.vhd