firtool-1.113.0

What's Changed

• [LLHD] Update LowerProcesses pass to work with process results by @fabianschuiki in #8387
• [FlattenMemRef] Flatten MemRef AllocaOp by @KelvinChung2000 in #8352
• [FIRRTL] Add a BindOp by @rwy7 in #8384
• Bump LLVM to 9344b2196cbc36cdc577314bbb2b889606ba6820. by @mikeurbach in #8404

New Contributors

• @KelvinChung2000 made their first contribution in #8352

Full Changelog: firtool-1.112.0...firtool-1.113.0

firtool-1.112.0

What's Changed

• [FIRRTL] Add doNotPrint flag to InstanceOp by @rwy7 in #8331
• [FirRegLowering] Add limit to number of ifs generated by @rwy7 in #8313
• [LowerToHW] Lower all op bodies in parallel by @rwy7 in #8383
• [MooreToCore] Lower moore.array_create Op by @AnnuCode in #8364
• [FIRRTL] Add fprintf operation by @uenoku in #8346
• [HWMemSimImpl] Avoid generation of 0 bit Value by @prithayan in #8393

New Contributors

• @AnnuCode made their first contribution in #8364

Full Changelog: firtool-1.111.1...firtool-1.112.0

firtool-1.111.1

What's Changed

• [Calyx] Canonicalizations that skip scf.execute_regions by @jiahanxie353 in #8358
• [SCFToCalyx] If op with sequential condition bug fix by @jiahanxie353 in #8341
• [FIRRTL] Fix: Enforce flat namespace for modules by @Jatin-exe in #8345
• [RTG] Add immediate type and attribute by @maerhart in #8314
• [RTGTest] Switch to new immediate types by @maerhart in #8315
• [PyRTG] Switch to new immediates by @maerhart in #8316
• [RTG] Add int_to_immediate op by @maerhart in #8318
• [LLHD] Make probes side-effect-free in graph regions by @fabianschuiki in #8372
• [LLHD] Hoist drives out of processes by @fabianschuiki in #8302
• [FIRRTL] Add printf widths, reject unknown by @seldridge in #8378
• [FIRRTL] Add {{HierarchicalModuleName}} support by @seldridge in #8380

New Contributors

• @Jatin-exe made their first contribution in #8345

Full Changelog: firtool-1.111.0...firtool-1.111.1

firtool-1.111.0

What's Changed

• [DOC] Add missing passes by @fhunstock-semron in #8344
• [FIRRTL] Add FormatStringType by @seldridge in #8342
• [AffineParallelOpUnparallelize][Calyx] Affine parallel loop unparallelize to nested for and parallel loop by @jiahanxie353 in #8340
• [LowerToHW] Lower PrintfOp w/ TimeOp by @seldridge in #8343
• [Seq] Fix width errors in HWMemSimImpl by @seldridge in #8351
• [FIRRTL] Add simulation op and parser support by @fabianschuiki in #8311
• [FIRRTL] Lower firrtl.simulation to verif.simulation by @fabianschuiki in #8312
• [LowerToHW] Add '0' to format string width by @seldridge in #8354
• [FIRRTL] Fold regreset to its reset value iff the type matches by @rwy7 in #8349
• [RTGTest] Fix CMake flag propagation for downstream by @maerhart in #8317
• [firtool] Bump "next" FIRRTL version to 5.1.0 by @seldridge in #8355
• [circt-reduce] Add bytecode import/export by @seldridge in #8347
• [FIRRTL] Sink fstring.time in LowerLayers by @seldridge in #8357

New Contributors

• @fhunstock-semron made their first contribution in #8344

Full Changelog: firtool-1.110.0...firtool-1.111.0

firtool-1.110.0

What's Changed

• [FIRRTL][AdvancedLayerSink] Add the ability to sink ops by cloning by @rwy7 in #8308
• [AffineToSCF][Calyx] Lower Affine to SCF for Calyx by @jiahanxie353 in #8323
• [LowerToBMC] Add comb as a dialect dependency by @TaoBi22 in #8326
• [OM] Add missing CAPI omTypeIsAMapType by @unlsycn in #8321
• [SCFToCalyx] If op with sequential condition by @jiahanxie353 in #7687
• [LowerSMTToZ3LLVM] Change printf type provided to lookupOrCreateFn by @TaoBi22 in #8327
• [FIRRTL] Canonicalize Assert(clk, p, e) when p == e by @rwy7 in #8320
• [SV] Add preprocessor include op by @rwy7 in #8329
• [circt-bmc] add rising clocks only mode by @TaoBi22 in #8330
• [SMT] expand Z3 library check in integration tests by @TaoBi22 in #8333
• [Python] Add binding for OutputFileAttr filename. by @mikeurbach in #8337
• [verif] add booth contract example by @leonardt in #8319
• [ExportVerilog] Back-annotate output file attributes during export. by @mikeurbach in #8338
• Bump LLVM to 4d5a963eaf6ad209487a321dee7f0cd2a0f98477. by @mikeurbach in #8336

Full Changelog: firtool-1.109.0...firtool-1.110.0

firtool-1.109.0

What's Changed

• [Transforms][circt-synth] Add HierarchicalRunner pass by @uenoku in #8254
• [LLHD] Add pass to hoist probes out of processes by @fabianschuiki in #8284
• [LowerSCFToCalyx] Lower Arith SubFOp by @jiahanxie353 in #8285
• [ESI Runtime] Color output formatting by @teqdruid in #8287
• Bump LLVM to 4fd5d935a3d30d20aed7697be5d8bb76dae8eab6. by @mikeurbach in #8288
• [SCFToCalyx] Arith FPToSI lowering and its emit by @jiahanxie353 in #8290
• [ESI Runtime] Use CLI11 for commandline tools arg parsing by @teqdruid in #8289
• [SCFToCalyx] Support Arith sitofp lowering and its emit by @jiahanxie353 in #8293
• [SCFToCalyx] Lower Arith Bitcast by @jiahanxie353 in #8294
• [circt-synth] Partially lower Comb operations and run canonicalizations by @uenoku in #8218
• [ESI] Add RemoveSnoopOp conversion pattern by @teqdruid in #8297
• [LLHD] Allow processes to yield results by @fabianschuiki in #8298
• [circt-test] fix SymbiYosys integration test by @unlsycn in #7886
• [Verif] Add multiplier integration test, fix bug in lower contracts by @leonardt in #8300
• [ESI] Simple FromHost DMA engine by @teqdruid in #8305
• [sim] Add emission for plusargs for UPF simulations by @youngar in #8301
• Bump LLVM to d90423e310482bdbc731242fa25dcb3dd44e69de. by @mikeurbach in #8306
• [SCFToCalyx] Arith DivFOp lowering and its emit by @jiahanxie353 in #8296

Full Changelog: firtool-1.108.0...firtool-1.109.0

firtool-1.108.0

What's Changed

• [MemoryBanking] Should not overwrite banking factor/dimension when resolving attribute values by @jiahanxie353 in #8267
• [LLHD] Add dedicated Mem2Reg pass by @fabianschuiki in #8244
• [ESI][XRT] Implement "Indirect MMIO" by @teqdruid in #8273
• [ImportVerilog] Add option to lower always @* as always_comb by @fabianschuiki in #8271
• [LLHD] Support conditional drives in mem2reg by @fabianschuiki in #8278
• [ESI][BSP] Simple ToHost DMA engine by @teqdruid in #8207
• [LLHD] Support drives with delta delay in mem2reg by @fabianschuiki in #8279
• [AffineParallelUnroll] Fix empty map lookup; move canonicalization passes before MemoryConflictResolver by @jiahanxie353 in #8282
• [circt-verilog-lsp-server] Add Verilog Language Server by @uenoku in #8234
• [SMT][CAPI] Add more SMT C API by @Clo91eaf in #8274
• [MemoryBanking] Memory banking supports multiple banking factors/dimensions config by @jiahanxie353 in #8277
• [Python] Declare a separate sub-target for support sources by @maerhart in #8243
• [sim] Add emission for plusargs for UPF simulations by @youngar in #8272

Full Changelog: firtool-1.107.0...firtool-1.108.0

firtool-1.107.0

What's Changed

• [Calyx] Unroll Affine ParallelOp to multiple SCF ExecuteRegionOps by @jiahanxie353 in #8248
• [Calyx] Change calyx.parallel to calyx.unroll in the test cases by @jiahanxie353 in #8251
• [Calyx] Canonicalize SCF IndexSwitch after AffineParallelUnroll by @jiahanxie353 in #8249
• [Calyx] virtual dtor to properly destruct derived classes by @dtzSiFive in #8252
• [SCFToCalyx] Update the lowering of SCF ParallelOp after AffineParallelUnroll pass by @jiahanxie353 in #8250
• [verif.contract] add sby integration test by @leonardt in #8237
• [Arcilator] Allow running verif.simulation ops by @fabianschuiki in #8233
• Bump LLVM for index CAPI by @maerhart in #8240
• [RTG] Add on_context and context_switch operations by @maerhart in #8150
• [RTG][Elaboration] Add support for context operations by @maerhart in #8151
• [RTG] Custom assembly format for 'rtg.test' operation by @maerhart in #8188
• [RTG] Add interleave_sequences op by @maerhart in #8189
• [RTG][Elaboration] Use malloc instead of IR for virtual registers and labels by @maerhart in #8194
• [RTG][Elaboration] Support interleave_sequences, factor our sequence inlining and label resolution by @maerhart in #8198
• [RTG][InlineSequences] Support interleave_sequences by @maerhart in #8199
• [RTG][CAPI] Expose getter for bag and set element type by @maerhart in #8227
• [PyRTG] Wrapper around SSA values and label support by @maerhart in #8228
• [PyRTG] Support sets by @maerhart in #8229
• [PyRTG] Support integers by @maerhart in #8235
• [PyRTG] Support bags by @maerhart in #8236
• [PyRTG] Support sequences by @maerhart in #8238
• [PyRTG] Support targets and test arguments by @maerhart in #8239
• [RTG] Move immediate type tablegen base to RTG dialect by @maerhart in #8242
• [PyRTG] Add immediates and registers by @maerhart in #8247
• [Verif] Change simulation exit code to success boolean by @fabianschuiki in #8253
• [LLHD][Sig2Reg] Support integer signal aliasing by @maerhart in #8261
• [FIRRTL] Add a folder for add property op by @mtsokol in #8200
• [circt-synth] Load dialects that firtool emits by @uenoku in #8257
• Bump LLVM to 6bfedfa0ba31a8ac8fd7fcfd2d33afaa5eabe0e5. by @mikeurbach in #8264
• [FIRRTL] Add folder for mul property op by @mtsokol in #8222
• [ExportSMTLIB] Implement ExportSMTLIB C API by @Clo91eaf in #8263
• [Calyx] LICM after Affine ParallelOp unrolling by @jiahanxie353 in #8256
• [FlattenMemRef] Flatten MemRef ReshapeOp when its source memory reference is flattened in other passes by @jiahanxie353 in #8265

New Contributors

• @mtsokol made their first contribution in #8200

Full Changelog: firtool-1.106.0...firtool-1.107.0

firtool-1.106.0

What's Changed

• [HW] Resolve ambiguous array_slice documentation by @maerhart in #8202
• [ESI][BSP] Bunch of small fixes and changes by @teqdruid in #8206
• [FIRRTL][LowerToHW] Lower contract ops by @fabianschuiki in #8159
• [circt-test] Add support for contracts by @fabianschuiki in #8166
• [MooreToCore]Fix a crash caused by block args as observed values for llhd.wait. by @hailongSun2000 in #8210
• [ImportVerilog] Fix assertion with constant folding by @likeamahoney in #8213
• [firtool] Add an option to emit HW MLIR into file by @uenoku in #8169
• [Verif] Mark SymbolicValueOp result as MemAlloc by @fabianschuiki in #8208
• [NFCI] Align cmake slightly more to mlir example by @darthscsi in #8217
• [RTG] Move immediates to RTG from RTGTest by @darthscsi in #8216
• [Moore] Mark wait_event with side-effect even if it is empty by @maerhart in #8220
• [LLHD] Add canonicalizer for ProcessOp by @maerhart in #8221
• Bump LLVM to 289b17635958d986b74683c932df6b1d12f37b70. by @mikeurbach in #8225
• [RTG] Add the PyRTG frontend by @maerhart in #8187
• [Verif] Add simulation op by @fabianschuiki in #8224
• [LLHD] Don't implement BranchOpInterface for WaitOp by @maerhart in #8241

New Contributors

• @likeamahoney made their first contribution in #8213

Full Changelog: firtool-1.105.0...firtool-1.106.0

firtool-1.105.0

What's Changed

• [RTG] Populate pipeline with new passes by @maerhart in #8139
• [RTG] Add label visibility API by @maerhart in #8140
• [RTGTest] Add integer register type API by @maerhart in #8141
• [RTGTest] Add the last remaining ops for RV32I by @maerhart in #8142
• [HW] Add array_concat of one element folder by @maerhart in #8181
• [MooreToCore] Convert SCF ops inside llhd.process to CF by @maerhart in #8175
• [MooreToCore] Don't insert wait event checks if all detects are AnyChange by @maerhart in #8178
• [MooreToCore] Properly handle OOB accesses of moore.extract by @maerhart in #8182
• [NFC][Verif] Clarify symbolic_value semantics by @TaoBi22 in #8177
• [circt-verilog] Fix negative Rest timing by @maerhart in #8174
• [circt-verilog] Add LLHD lowering pipeline by @maerhart in #8179
• [MooreToCore] Branch to resume block instead of wait block by @maerhart in #8184
• [CombToAIG] Add support for div/mod operations by @uenoku in #8130
• [ESI Runtime] Pluggable channel engines by @teqdruid in #8167
• [MooreToCore] Add nested moore.conditional support by @AndreyVV-100 in #8125
• [LLHD] Removing llhd-sim tests by @teqdruid in #8036
• [RTG] Custom parser/printer for sequence op and type for sequence families by @maerhart in #8146
• [RTG] Separate operation for sequence randomization and randomized sequence type by @maerhart in #8147
• [RTG] Support partial sequence substitutions by @maerhart in #8148
• [RTG] Add operation to get a random number within a range by @maerhart in #8149
• [FIRRTL] FART: allow modules to be in multiple domains at once by @youngar in #8172
• [ESI][BSP] Service implementation via selectable engine by @teqdruid in #8186
• [FIRRTL] Disallow reading from property ports by @youngar in #8191
• [ImportVerilog] Fix bit slicing into variables declared with offset by @maerhart in #8190
• [FIRRTL] Add require and ensure intrinsics by @fabianschuiki in #8154
• [LLHD][TCM] Ignore processes with CFG loops within a TR by @maerhart in #8196
• [FIRRTL] Add contract declaration by @fabianschuiki in #8156
• [FIRRTL] Fix hasDontTouch crash on non-module block args by @fabianschuiki in #8157
• [FIRRTL][IMDCE] Support operations with blocks by @fabianschuiki in #8158
• [ImportVerilog]Support real math functions. by @hailongSun2000 in #8192
• [ESI][BSP] Emit engine records by @teqdruid in #8204
• [ESI][Runtime] Throw unknown engine error lazily by @teqdruid in #8205
• [FIRRTL] Add optional yaml parameter to view intrinsic, op by @dtzSiFive in #8203

Full Changelog: firtool-1.104.0...firtool-1.105.0