[LowerToHW] Add '0' to format string width #8354
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Add a zero width to all format string substitutions when lowering from FIRRTL to HW/SV. E.g., this will lower `%x` into `%0x`. This is almost always preferred and avoids the need for (right now) adding width specifiers to Chisel and FIRRTL. While we would like to do this, we don't want to do it as passthrough from Chisel where Chisel users write Verilog format substitutions. As @jackkoenig and I got to bottom of, there are non-standard format specifiers that people might want (e.g., `%-` for left justified) that tools support differently and we would like to figure out how to actually lower these if they matter. Signed-off-by: Schuyler Eldridge <[email protected]>
seldridge
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rwy7
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Mar 27, 2025
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Mar 27, 2025
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Add a zero width to all format string substitutions when lowering from FIRRTL to HW/SV. E.g., this will lower
%xinto%0x. This is almost always preferred and avoids the need for (right now) adding width specifiers to Chisel and FIRRTL. While we would like to do this, we don't want to do it as passthrough from Chisel where Chisel users write Verilog format substitutions.As @jackkoenig and I got to bottom of, there are non-standard format specifiers that people might want (e.g.,
%-for left justified) that tools support differently and we would like to figure out how to actually lower these if they matter.