issue with BlackBox in Chisel 2

the issue with the Blackboxing in Chisel2 is simulation with the C backend. Generating RTL works fine. The problem in simulation is that the the testing system doesn't know the functionality of the blackbox. In Chisel3 we can point the Verilog source and ask Verilator to generate the C++ code to use this in testing purpose but in Chisel2 I think we can not do it. So I looked in to mingle with the generating c++ code but it seems everytime we invoke sbt it regenerate the c++ code so all manual modification get lost. Then I looked into porting c++ code in to Scala and it seems its doable but not easy. We can port the c++ model of our verilog RTL through JNI (Java Native Interface) and run the simulation. The easiest solution I see is the GrayBox-ing instead of BlackBox-ing. If you consider this approach and dump it please let me know. We can implement the same functionality in Scala and Verilog RTL, We can run the backend c simulation using the scala model. Then we can get the converted RTL from scala model (Golden) and verify it against the Verilog RTL that we want to Synthesize. We can easily do this in Synosys VCS and check the functional coverage to make sure everything is correct. This is pretty much similar to custom digital circuit verification where we have a golden RTL which has the functionality and the spice netlist schematic which we are going to implement at the end.