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Welcome to the riscv-sodor wiki!

Parameterization

Code

Currently there are two development branches and my commits to either of them

• master
• fpga

Apart from the above main repository changes have also been to made to the following forked repositories to get support for not supported features:

• riscv-fesvr
• glip

Pull request with following deliverables has already been merged upstream : https://github.com/ucb-bar/riscv-sodor/pull/23

• priv1.10
• chisel3
• support for limited features of debug spec v0.13

Deliverables

Completed

• priv1.10
• chisel3
• debug spec v0.13
• Tilelink integration (code reuse from rocket)
• Port to FPGA
• Microarchitecture diagrams

Not completed

• Support to detect misaligned address
• Documentation along with comments to source

Future work

1. Integrate glip into sodor on fpga to help establish a communication link with fesvr(x86)
2. Refactor source that was used to get support for sodor on fpga to make it more understandable as it is currently in a deep mess
3. Complete deliverables, pending tasks as listed above
4. Pull request for code not yet merged upstream i.e. tilelink,fpga related,documentation with microarchitecture diagrams
5. Get changes in riscv-fesvr upstream
6. Support for Open Soc Debug because otherwise its difficult to debug target especially if its running on fpga

Detailed description about the key learnings and challenges would be available here https://codelec.github.io/