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Diplomacy
Diplomacy is a parameter negotiation framework for generating parameterized protocol implementations. Given a description of sets of inter-connected master and slave devices, and a bus protocol template, Diplomacy cross-checks the requirements of all connected devices, negotiates free parameters, and supplies final parameter bindings to adapters and endpoints for use in their own hardware generation processes.Beyond confirming the mutual compatibility of the system endpoints, Diplomacy enables them to specialize themselves based on knowledge of the other endpoints included in a particular system.
TileLink is a highly-parameterized chip-scale shared-memory interconnect protocol standard. The protocol is hierarchically composable and guaranteed to deadlock-free at the transaction level. The implementation of TileLink in the Rocket Chip generator exploits Diplomacy to supply a heterogeneous level of protocol conformance across the interconnect, specialized for the capabilities of devices connected to certain buses.
While Chisel makes it easy to write parameterized design components, it provides no particular functionality related to parameterization other than that built in to Scala itself. Diplomacy extends Chisel, being a library that provides a parameter negotiation framework for generating hardware connected to a shared interconnection network. Operating on a description of a SoC design expressed as a directed graph of interconnected nodes, Diplomacy cross-checks a set of protocol-specific requirements over relevant subsets of the interconnect. Diplomacy allows for the negotiation of any free parameters within a protocol, such as particular data or control wire widths, customizing them based on the topology expressed by each sub-graph of communicating nodes.
After enabling all the endpoint nodes to negotiate protocol parameter values, Diplomacy then supplies concrete parameter bindings to individual adapters and endpoint generators, which can use them to drive their own individual hardware generation processes. Diplomacy is thus an example of two-phase hardware elaboration. The first phase is parameter negotiation, wherein the topology of the graph is discovered and the nodes negotiate the value of the parameters on every edge. The second phase is concrete module generation, in which the Chisel compiler is invoked on the module hierarchy associated with the node graph. As each Chisel module is elaborated, it can make use of the diplomatic parameters that have been precomputed by its associated diplomatic nodes.
- nodes - points in the design where diplomatic parameters are used to emit hardware. Nodes may participate in multiple edge pairings and may have a single type of interface (an endpoint node), or may forward from one type to the other (an adapter node); and
- edges - a directed pairing of master and slave interfaces, where the source node represents a master interface and sink node represents the matching slave interfaces. Edges communicate a protocol-specific set of parameters between masters and slaves, and these parameters are specified to flow either outward (from source to sinks), or inward (from sinks to sources). Edges are used to elaborate the wires that actually create the physical connections in the final design, in the form of wires or module IOs. A module may have multiple nodes and a node may have multiple edges.
Beyond confirming the mutual compatibility of the system endpoints, Diplomacy enables them to specialize themselves based on knowledge of the other endpoints included in a particular system. Each node supplies its associated generator with a set of edges that contain a view of the interconnect as seen from that node. By accessing the parameter values available on a particular edge, the generator can specialize its behavior according to the capabilities of that edge. For example, it may size the hardware it generates internally according to the negotiated width parameters supplied by the edge.
For an example Rocket Chip design's diplomatic graph and further explanations, please open up slides given in [1].
Current version of the package within rocket-chip is found here.
Further details in the context of LowRISC may be found in [3].
TileLink is a chip-scale interconnect protocol standard for providing multiple processing elements with coherent access to shared memory and other memory-mapped devices. Specifically, TileLink is designed to be deployed in a System-on-Chip (SoC) to connect general-purpose multiprocessors, co-processors, accelerators, caches, DMA engines, memory controller, and simple or complex peripheral devices. The protocol is optimized to be efficient when deployed within tightly-coupled, low-latency SoC buses. It can also be implemented over hierarchically-composable, point-to-point networks, and can scale down to interface with low-throughput slave devices or scale up to provide high-throughput interconnects. TileLink provides coherent access for an arbitrary mix of caching or non-caching masters to a physically-addressed, shared-memory system. Cache coherence is maintained by a customizable, MOESI-equivalent protocol based on hierarchical composition. The protocol supports out-of-order transaction completion to improve throughput for concurrent operations. Protocol can be implemented as either update or invalidation based. Rocket-Chip currently uses an invalidation based coherence protocol.
The TileLink specification maps closely onto the abstractions used by Diplomacy. TileLink agents are semantically equivalent to diplomatic graph nodes. TileLink links are semantically equivalent to diplomatic graph edges.
Within a link, TileLink contains five logical channels, which correspond to the priorities of the messages that they carry. Each channel consists of control and data signals that are transmitted using a decoupled, ready-valid based handshaking protocol. TileLink memory operations comprise a series of messages sent over channels, obeying certain transaction rules (e.g. all requests have responses). To avoid deadlock, TileLink specifies a priority amongst the channels’ messages that must be strictly enforced. The prioritization of messages across channels is A « B « C « D « E, in order of increasing priority. Channels are directional, in that each passes messages either from master to slave interface or from slave to master interface.
TileLink provides formally-verifiable deadlock freedom for any SoC consisting of compliant network and endpoint implementations.
Diplomacy allows us to avoid specifying any parameters that can instead be inferred from the declarative description of the graph. Consider the example of an arbiter that takes N inputs. We do not have to explicitly state the cardinality of N anywhere in the code base, and the value of N that is inferred from the graph topology during the first phase of elaboration is automatically propagated to both the arbiter generator as well as to all downstream edges used to parameterize wire widths during the second phase.
Beyond serving as an unambiguous source of cardinality information, the diplomatic graph provides generators with knowledge of the capabilities of the other nodes in the system with which they are interconnected.
Master nodes can see the capabilities of all slaves whose memory-mapped addresses are visible to them. This view can be used to determine whether a particular memory operation will be legal to issue, either at Chisel compile time, or within the generated hardware control logic.
Conversely, slaves can see the capabilities of all masters whose operations can reach them.
The properties of the the TileLink protocol (given in detail in [1]) have the advantage of ensuring that design changes encompassing certain transformations on an extant diplomatic graph are guaranteed to produce another correct graph and implementation. These transformations are all based on injecting new sub-graphs that preserve the Directed Acyclic Graph property. These three particular transformations have shaped the structure of the Rocket Chip codebase:
- combinational composition - multiple adapter nodes are composed in a linear sequence;
- sequential composition - exploits the fact that the decoupled nature of the TileLink channels make it trivial to insert an interstitial adapter that is a queue; and
- hierarchical composition - can swap out any node of the diplomatic graph for an entirely new subgraph that maintains the same properties at its inward and/or outward attachment points.
Additional simple example may be found in [3].
Rocket tile interface nodes: tile/RocketTile.scala:43
RocketTile is a LazyModule, the actual implementation is instantiated tile/RocketTile.scala:95
Core instantiation: tile/RocketTile.scala:103
For practical purposes, in order to modify the implementation of the module, you’ll typically want to modify the implementation module (LazyModuleImp / BaseTileModuleImp / etc). You can see above that the implementation of the core is done in line 103, which is inside the BaseTileModuleImp.
LazyModule (diplomacy) -- LazyModule is outer -- then inside is an implementation -- diplomacy negotiates between
In Diplomacy language, the RocketTile is a node. In TileLink language RocketTile is also an agent (a TileLink agent is semantically equivalent to a Diplomacy graph node). A Diplomacy node may contain many different directed links to other nodes. In Diplomacy, those links are called edges, in TileLink, they're called links.
- Henry Cook, Wesley Terpstra, and Yunsup Lee. 2017. Diplomatic Design Patterns: A TileLink Case Study. In Proceedings of First Workshop on Computer Architecture Research with RISC-V, Boston, MA USA, October 2017 (CARRV’17), 7 pages
- Wei Song, Diplomacy and TileLink from the Rocket Chip, lowRISC website, 2018
- Edmond Cote, Parameters and lazy modules, Edmond Cote's Blog, 2017