Add checking of success to force an error if not

PyFPGA · Jun 30, 2024 · daf7f7c · daf7f7c
1 parent f027f22
commit daf7f7c
Showing 1 changed file with 4 additions and 0 deletions.
diff --git a/pyfpga/templates/vivado.jinja b/pyfpga/templates/vivado.jinja
@@ -50,6 +50,8 @@ open_project {{ PROJECT }}
 reset_run synth_1
 launch_runs synth_1
 wait_on_run synth_1
+#report_property [get_runs synth_1]
+if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 }
 
 {{ POSTSYN }}
 {% endif %}
@@ -60,6 +62,8 @@ wait_on_run synth_1
 reset_run impl_1
 launch_runs impl_1
 wait_on_run impl_1
+#report_property [get_runs impl_1]
+if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 }
 
 {{ POSTPAR }}
 {% endif %}