Fix pylint complaint

PyFPGA · Jun 30, 2024 · f027f22 · f027f22
1 parent f403d88
commit f027f22
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/tests/projects/support.py b/tests/projects/support.py
@@ -39,7 +39,7 @@
     sys.exit('ERROR: something does not work as expected')
 except SystemExit:
     raise
-except:
+except Exception:
     pass
 
 try:
@@ -55,7 +55,7 @@
     sys.exit('ERROR: something does not work as expected')
 except SystemExit:
     raise
-except:
+except Exception:
     pass
 
 try:
@@ -71,7 +71,7 @@
     sys.exit('ERROR: something does not work as expected')
 except SystemExit:
     raise
-except:
+except Exception:
     pass
 
 print('INFO: checking Verilog Support')
@@ -109,7 +109,7 @@
         sys.exit('ERROR: something does not work as expected')
     except SystemExit:
         raise
-    except:
+    except Exception:
         pass
 
     print('* VHDL Support')