Modify directory for data slicer (#90)

* rtl: mode data_slicer to other directory * bender: update data directories * test: mv directory
KULeuven-MICAS · Oct 19, 2024 · 3648c90 · 3648c90
1 parent e81ed7c
commit 3648c90
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Showing 3 changed files with 6 additions and 3 deletions.
diff --git a/Bender.yml b/Bender.yml
@@ -15,13 +15,13 @@ sources:
       - rtl/common/fifo_buffer.sv
       - rtl/common/reg_file_1w1r.sv
       - rtl/common/reg_file_1w2r.sv
-      # Level 1
-      - rtl/common/data_slicer.sv
       #---------------------------
       # Common Modules
       #---------------------------
       # Level 0
       - rtl/data_formatter/update_counter.sv
+      # Level 1
+      - rtl/data_formatter/data_slicer.sv
       #---------------------------
       # Encoder
       #---------------------------

diff --git a/rtl/common/data_slicer.sv → rtl/data_formatter/data_slicer.sv b/rtl/common/data_slicer.sv → rtl/data_formatter/data_slicer.sv
diff --git a/tests/test_data_slicer.py b/tests/test_data_slicer.py
@@ -210,7 +210,10 @@ async def data_slicer_dut(dut):
     ],
 )
 def test_data_slicer(simulator, parameters, waves):
-    verilog_sources = ["/rtl/common/fifo_buffer.sv", "/rtl/common/data_slicer.sv"]
+    verilog_sources = [
+        "/rtl/common/fifo_buffer.sv",
+        "/rtl/data_formatter/data_slicer.sv",
+    ]
 
     toplevel = "data_slicer"