This is the GitHub organization for the MICAS research group at KU Leuven. Here you can find open-source projects made by us and our collaborators.

Snax is an end-to-end, open-source multi-accelerator cluster design framework. It consists of the snax-mlir compile toolchain and the snax cluster hardware framework.

ZigZag targets rapid DSE for DNN accelerator platforms supporting an broad set of hardware architectures and workload scheduling scenarios beyond other existing frameworks.
The latest version of ZigZag includes support for modeling of analog and digital in-memory computing accelerators and estimating both peak/workload performance at the macro and system level.

Stream is an extension of ZigZag capable of modeling multi-core DNN acceleration employing fine-grained layer-fused processing.

ZigZag-LLM is a framework to rapidly model Large Language Models on dedicated, single-core accelerators and facilitates early identification of energy bottlenecks within the hardware architecture.

DeFiNes extends ZigZag to enable the DSE of cross-layer depth-first scheduling (a.k.a. layer fusion, or cascaded execution)

HTVM is a neural network compiler based on Dory and TVM that allows for efficient neural network deployment on heterogenous TinyML platforms with scratchpad-memory accelerators.

V. Jain, S. Giraldo, J. D. Roose, L. Mei, B. Boons and M. Verhelst, "TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge," in IEEE Journal of Solid-State Circuits, doi: 10.1109/JSSC.2023.3236566.

V. Jain, S. Giraldo, J. D. Roose, B. Boons, L. Mei and M. Verhelst, "TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge," 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2022, pp. 20-21, doi: 10.1109/VLSITechnologyandCir46769.2022.9830409.

K. Ueyoshi et al., "DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC," 2022 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731716.

P. Houshmand et al., "DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge," in IEEE Journal of Solid-State Circuits, vol. 58, no. 1, pp. 203-215, Jan. 2023, doi: 10.1109/JSSC.2022.3214064.

N. Shah, L. I. G. Olascoaga, S. Zhao, W. Meert and M. Verhelst, "DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm," in IEEE Journal of Solid-State Circuits, vol. 57, no. 8, pp. 2586-2596, Aug. 2022, doi: 10.1109/JSSC.2021.3134897.

NN. Shah, W. Meert and M. Verhelst, "DPU-v2: Energy-efficient execution of irregular directed acyclic graphs," 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), Chicago, IL, USA, 2022, pp. 1288-1307, doi: 10.1109/MICRO56248.2022.00090.