Skip to content

Commit

Permalink
Floating address on quadrant + remove snitch's tlb + remove inter-qua…
Browse files Browse the repository at this point in the history 
…drant xbar (#22)

* Remove tile_id; add chip_id in the occamy_pkg

* Bug Fix

* Bug Fix

* Floating address for quadrant

* Disable TLB inside quadrant

* Remove inter-quadrant xbar
  • Loading branch information
@IveanEx
IveanEx authored Aug 28, 2024
1 parent 5f0d5bb commit 71556ee
Show file tree
Hide file tree
Showing 12 changed files with 89 additions and 125 deletions.
4 changes: 3 additions & 1 deletion hw/occamy/occamy_pkg.sv.tpl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,9 @@ package ${name}_pkg;
localparam logic [15:0] PartNum = 2;
localparam logic [31:0] IDCode = (dm::DbgVersion013 << 28) | (PartNum << 12) | 32'h1;

typedef logic [5:0] tile_id_t;

localparam int unsigned ChipIdWidth = ${hemaia_multichip["chip_id_width"]};
typedef logic [ChipIdWidth-1:0] chip_id_t;

typedef logic [AddrWidth-1:0] addr_t;
typedef logic [NarrowUserWidth-1:0] user_narrow_t;
Expand Down
25 changes: 14 additions & 11 deletions hw/occamy/occamy_quadrant_s1.sv.tpl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ module ${name}_quadrant_s1
input logic clk_i,
input logic rst_ni,
input logic test_mode_i,
input tile_id_t tile_id_i,
input chip_id_t chip_id_i,
input logic [NrCoresS1Quadrant-1:0] meip_i,
input logic [NrCoresS1Quadrant-1:0] mtip_i,
input logic [NrCoresS1Quadrant-1:0] msip_i,
Expand All @@ -44,18 +44,21 @@ module ${name}_quadrant_s1
input ${soc_narrow_xbar.in_s1_quadrant_0.rsp_type()} quadrant_narrow_out_rsp_i,
input ${soc_narrow_xbar.out_s1_quadrant_0.req_type()} quadrant_narrow_in_req_i,
output ${soc_narrow_xbar.out_s1_quadrant_0.rsp_type()} quadrant_narrow_in_rsp_o,
output ${quadrant_inter_xbar.in_quadrant_0.req_type()} quadrant_wide_out_req_o,
input ${quadrant_inter_xbar.in_quadrant_0.rsp_type()} quadrant_wide_out_rsp_i,
input ${quadrant_inter_xbar.out_quadrant_0.req_type()} quadrant_wide_in_req_i,
output ${quadrant_inter_xbar.out_quadrant_0.rsp_type()} quadrant_wide_in_rsp_o,
output ${soc_wide_xbar.in_quadrant_0.req_type()} quadrant_wide_out_req_o,
input ${soc_wide_xbar.in_quadrant_0.rsp_type()} quadrant_wide_out_rsp_i,
input ${soc_wide_xbar.out_quadrant_0.req_type()} quadrant_wide_in_req_i,
output ${soc_wide_xbar.out_quadrant_0.rsp_type()} quadrant_wide_in_rsp_o,
// SRAM configuration
input sram_cfg_quadrant_t sram_cfg_i
);

// Calculate cluster base address based on `tile id`.
addr_t cluster_base_offset;
assign cluster_base_offset = {chip_id_i, ClusterBaseOffset[AddrWidth-ChipIdWidth-1:0]};

addr_t [${nr_clusters-1}:0] cluster_base_addr;
% for i in range(nr_clusters):
assign cluster_base_addr[${i}] = ClusterBaseOffset + tile_id_i * NrClustersS1Quadrant * ClusterAddressSpace + ${i} * ClusterAddressSpace;
assign cluster_base_addr[${i}] = cluster_base_offset + ${i} * ClusterAddressSpace;
%endfor

// Define types for IOTLBs
Expand All @@ -65,7 +68,7 @@ module ${name}_quadrant_s1
logic clk_quadrant, rst_quadrant_n;
logic [3:0] isolate, isolated;
logic ro_enable, ro_flush_valid, ro_flush_ready;
logic [${ro_cache_regions-1}:0][${quadrant_inter_xbar.in_quadrant_0.aw-1}:0] ro_start_addr, ro_end_addr;
logic [${ro_cache_regions-1}:0][${soc_wide_xbar.in_quadrant_0.aw-1}:0] ro_start_addr, ro_end_addr;
%if narrow_tlb_cfg:
logic narrow_tlb_enable;
tlb_entry_t [${narrow_tlb_entries-1}:0] narrow_tlb_entries;
Expand Down Expand Up @@ -154,7 +157,7 @@ module ${name}_quadrant_s1
.isolate(context, "isolate[3]", "wide_cluster_out_isolate", isolated="isolated[3]", atop_support=False, to_clk="clk_i", to_rst="rst_ni", use_to_clk_rst=True, num_pending=wide_trans) \
.cut(context, cuts_wideiwc_with_wideout)
#// Assert correct outgoing ID widths
assert quadrant_inter_xbar.in_quadrant_0.iw == wide_cluster_out_cut.iw, "S1 Quadrant and SoC IW mismatches."
assert soc_wide_xbar.in_quadrant_0.iw == wide_cluster_out_cut.iw, "S1 Quadrant and SoC IW mismatches."
%>

assign quadrant_wide_out_req_o = ${wide_cluster_out_cut.req_name()};
Expand All @@ -164,7 +167,7 @@ module ${name}_quadrant_s1
// Wide In + IW Converter //
////////////////////////////
<%
quadrant_inter_xbar.out_quadrant_0 \
soc_wide_xbar.out_quadrant_0 \
.copy(name="wide_cluster_in_iwc") \
.declare(context) \
.cut(context, cuts_wideiwc_with_wideout) \
Expand All @@ -185,7 +188,7 @@ module ${name}_quadrant_s1
.clk_i,
.rst_ni,
.test_mode_i,
.tile_id_i,
.chip_id_i,
.clk_quadrant_o (clk_quadrant),
.rst_quadrant_no (rst_quadrant_n),
.isolate_o (isolate),
Expand Down Expand Up @@ -228,7 +231,7 @@ module ${name}_quadrant_s1
%>

logic [9:0] hart_base_id_${i};
assign hart_base_id_${i} = HartIdOffset + tile_id_i * NrCoresS1Quadrant + NrCoresClusterOffset[${i}];
assign hart_base_id_${i} = HartIdOffset + NrCoresClusterOffset[${i}];

${cluster_name}_wrapper i_${name}_cluster_${i} (
.clk_i (clk_quadrant),
Expand Down
9 changes: 4 additions & 5 deletions hw/occamy/occamy_quadrant_s1_ctrl.sv.tpl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,7 @@ module ${name}_quadrant_s1_ctrl
input logic clk_i,
input logic rst_ni,
input logic test_mode_i,

input tile_id_t tile_id_i,
input chip_id_t chip_id_i,

// Quadrant clock and reset
output logic clk_quadrant_o,
Expand All @@ -33,8 +32,8 @@ module ${name}_quadrant_s1_ctrl
output logic ro_flush_valid_o,
input logic ro_flush_ready_i,

output logic [${ro_cache_regions-1}:0][${quadrant_inter_xbar.in_quadrant_0.aw-1}:0] ro_start_addr_o,
output logic [${ro_cache_regions-1}:0][${quadrant_inter_xbar.in_quadrant_0.aw-1}:0] ro_end_addr_o,
output logic [${ro_cache_regions-1}:0][${soc_wide_xbar.in_quadrant_0.aw-1}:0] ro_start_addr_o,
output logic [${ro_cache_regions-1}:0][${soc_wide_xbar.in_quadrant_0.aw-1}:0] ro_end_addr_o,

// Upward (SoC) narrow ports
output ${soc_narrow_xbar.in_s1_quadrant_0.req_type()} soc_out_req_o,
Expand All @@ -61,7 +60,7 @@ module ${name}_quadrant_s1_ctrl

// Upper half of quadrant space reserved for internal use (same size as for all clusters)
addr_t [0:0] internal_xbar_base_addr;
assign internal_xbar_base_addr = '{S1QuadrantCfgBaseOffset + tile_id_i * S1QuadrantCfgAddressSpace};
assign internal_xbar_base_addr = {chip_id_i, S1QuadrantCfgBaseOffset[AddrWidth-ChipIdWidth-1:0]};

// Controller crossbar: shims off for access to internal space
${module}
Expand Down
28 changes: 7 additions & 21 deletions hw/occamy/occamy_soc.sv.tpl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,8 @@
<%
cuts_narrow_to_quad = occamy_cfg["cuts"]["narrow_to_quad"]
cuts_quad_to_narrow = occamy_cfg["cuts"]["quad_to_narrow"]
cuts_quad_to_inter = occamy_cfg["cuts"]["quad_to_inter"]
cuts_inter_to_quad = occamy_cfg["cuts"]["inter_to_quad"]
cuts_wide_to_quad = occamy_cfg["cuts"]["wide_to_quad"]
cuts_quad_to_wide = occamy_cfg["cuts"]["quad_to_wide"]
cuts_narrow_to_cva6 = occamy_cfg["cuts"]["narrow_to_cva6"]
cuts_narrow_conv_to_spm_narrow_pre = occamy_cfg["cuts"]["narrow_conv_to_spm_narrow_pre"]
cuts_narrow_conv_to_spm_narrow = occamy_cfg["cuts"]["narrow_conv_to_spm_narrow"]
Expand Down Expand Up @@ -77,26 +77,12 @@ module ${name}_soc
// Crossbars //
///////////////

addr_t [${nr_s1_quadrants-1}:0] s1_quadrant_base_addr, s1_quadrant_cfg_base_addr;
% for i in range(nr_s1_quadrants):
assign s1_quadrant_base_addr[${i}] = ClusterBaseOffset + ${i} * S1QuadrantAddressSpace;
assign s1_quadrant_cfg_base_addr[${i}] = S1QuadrantCfgBaseOffset + ${i} * S1QuadrantCfgAddressSpace;
% endfor

// Crossbars
${module}

///////////////////////////////////
// Connections between crossbars //
///////////////////////////////////
<%
#// inter xbar -> wide xbar & wide xbar -> inter xbar
quadrant_inter_xbar.out_wide_xbar \
.change_iw(context, soc_wide_xbar.iw, "inter_to_wide_iw_conv_{}".format(i), max_txns_per_id=txns_wide_and_inter) \
.cut(context, cuts_wide_and_inter, name="inter_to_wide_cut_{}".format(i), to=soc_wide_xbar.in_quadrant_inter_xbar)
soc_wide_xbar.out_quadrant_inter_xbar \
.cut(context, cuts_wide_and_inter, name="wide_to_inter_cut_{}".format(i)) \
.change_iw(context, quadrant_inter_xbar.iw, "wide_to_inter_iw_conv_{}".format(i), to=quadrant_inter_xbar.in_wide_xbar, max_txns_per_id=txns_wide_and_inter)
#// narrow xbar -> wide xbar & wide xbar -> narrow xbar
soc_narrow_xbar.out_soc_wide \
.atomic_adapter(context, max_trans=max_atomics_wide, user_as_id=1, user_id_msb=soc_narrow_xbar.out_soc_wide.uw-1, user_id_lsb=0, n_cuts= cuts_withing_atomic_adapter_narrow_wide, name="soc_narrow_wide_amo_adapter") \
Expand Down Expand Up @@ -143,18 +129,18 @@ module ${name}_soc
narrow_in = soc_narrow_xbar.__dict__["out_s1_quadrant_{}".format(i)].cut(context, cuts_narrow_to_quad, name="narrow_in_{}".format(i))
narrow_out = soc_narrow_xbar.__dict__["in_s1_quadrant_{}".format(i)].copy(name="narrow_out_{}".format(i)).declare(context)
narrow_out.cut(context, cuts_quad_to_narrow, name="narrow_out_cut_{}".format(i), to=soc_narrow_xbar.__dict__["in_s1_quadrant_{}".format(i)])
#// inter xbar -> quad & quad -> pre xbar
wide_in = quadrant_inter_xbar.__dict__["out_quadrant_{}".format(i)].cut(context, cuts_inter_to_quad, name="wide_in_{}".format(i))
#// wide xbar -> quad & quad -> wide xbar
wide_in = soc_wide_xbar.__dict__["out_quadrant_{}".format(i)].cut(context, cuts_wide_to_quad, name="wide_in_{}".format(i))
#//wide_out = quadrant_pre_xbars[i].in_quadrant.copy(name="wide_out_{}".format(i)).declare(context)
wide_out = quadrant_inter_xbar.__dict__["in_quadrant_{}".format(i)].copy(name="wide_out_{}".format(i)).declare(context)
wide_out.cut(context, cuts_quad_to_inter, name="wide_out_cut_{}".format(i), to=quadrant_inter_xbar.__dict__["in_quadrant_{}".format(i)])
wide_out = soc_wide_xbar.__dict__["in_quadrant_{}".format(i)].copy(name="wide_out_{}".format(i)).declare(context)
wide_out.cut(context, cuts_quad_to_wide, name="wide_out_cut_{}".format(i), to=soc_wide_xbar.__dict__["in_quadrant_{}".format(i)])
%>\

${name}_quadrant_s1 i_${name}_quadrant_s1_${i} (
.clk_i (clk_i),
.rst_ni (rst_ni),
.test_mode_i (test_mode_i),
.tile_id_i (6'd${i}),
.chip_id_i (8'b0), // Temporary solution as the Chip ID is not provided yet
.meip_i ('0),
.mtip_i (mtip_i[${lower_core + nr_cores_s1_quadrant - 1}:${lower_core}]),
.msip_i (msip_i[${lower_core + nr_cores_s1_quadrant - 1}:${lower_core}]),
Expand Down
5 changes: 2 additions & 3 deletions hw/occamy/quadrant_s1_ctrl/occamy_quadrant_s1_reg.hjson.tpl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -122,6 +122,7 @@
% endfor

% for i, t in enumerate(("narrow", "wide")):
% if "{}_tlb_cfg".format(t) in occamy_cfg["s1_quadrant"]:
// Start ${t} TLB fields at regular offset
{ skipto: "${hex(0x800*(1+i))}" }
% for e in range(occamy_cfg["s1_quadrant"]["{}_tlb_cfg".format(t)].get("l1_num_entries", 1)):
Expand Down Expand Up @@ -186,9 +187,7 @@
},
{ reserved: 1 }
% endfor
% endif
% endfor



]
}
2 changes: 1 addition & 1 deletion target/rtl/cfg/cluster_cfg/snax_KUL_cluster.hjson
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@
cluster_base_hartid: 1,
addr_width: 48,
data_width: 64,
user_width: 5,
user_width: 3,
tcdm: {
size: 512, // 128K -> 512K
banks: 32,
Expand Down
2 changes: 1 addition & 1 deletion target/rtl/cfg/cluster_cfg/snax_KUL_xdma_cluster.hjson
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@
cluster_base_hartid: 1,
addr_width: 48,
data_width: 64,
user_width: 5,
user_width: 3,
tcdm: {
size: 512, // 128K -> 512K
banks: 32,
Expand Down
2 changes: 1 addition & 1 deletion target/rtl/cfg/cluster_cfg/snax_minimal_cluster.hjson
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
cluster_base_hartid: 1,
addr_width: 48,
data_width: 64,
user_width: 5, // clog2(total number of clusters)
user_width: 3, // clog2(total number of clusters)
tcdm: {
size: 128, // 128 kiB
banks: 32,
Expand Down
2 changes: 1 addition & 1 deletion target/rtl/cfg/cluster_cfg/snax_xdma_cluster.hjson
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
cluster_base_hartid: 1,
addr_width: 48,
data_width: 64,
user_width: 5, // clog2(total number of clusters)
user_width: 3, // clog2(total number of clusters)
tcdm: {
size: 128, // 128 kiB
banks: 32,
Expand Down
38 changes: 21 additions & 17 deletions target/rtl/cfg/occamy_cfg/snax_two_clusters.hjson
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,12 @@
{
// Remote CFG
// Remote CFG, about to be removed

is_remote_quadrant: false,
remote_quadrants: [],
// Multi-chip configuration
hemaia_multichip: {
chip_id_width: 8
}
addr_width: 48,
data_width: 64,
// XBARs
Expand All @@ -24,10 +29,8 @@
cuts: {
narrow_to_quad: 3,
quad_to_narrow: 3,
quad_to_pre: 1,
pre_to_inter: 1,
quad_to_inter: 1,
inter_to_quad: 3,
wide_to_quad: 3,
quad_to_wide: 3,
narrow_to_cva6: 2,
narrow_conv_to_spm_narrow_pre: 2,
narrow_conv_to_spm_narrow: 1,
Expand Down Expand Up @@ -74,7 +77,7 @@
rmq: 4,
},
narrow_xbar_slv_id_width: 4,
narrow_xbar_user_width: 5, // clog2(total number of clusters)
narrow_xbar_user_width: 3, // clog2(total number of clusters)
nr_s1_quadrant: 1,
s1_quadrant: {
// number of pending transactions on the narrow/wide network
Expand All @@ -88,16 +91,17 @@
max_trans: 32,
address_regions: 4,
}
narrow_tlb_cfg: {
max_trans: 32,
l1_num_entries: 8,
l1_cut_ax: true,
}
wide_tlb_cfg: {
max_trans: 32,
l1_num_entries: 8,
l1_cut_ax: true,
}
// TLB is disabled
// narrow_tlb_cfg: {
// max_trans: 32,
// l1_num_entries: 8,
// l1_cut_ax: true,
// }
// wide_tlb_cfg: {
// max_trans: 32,
// l1_num_entries: 8,
// l1_cut_ax: true,
// }
wide_xbar: {
max_slv_trans: 32,
max_mst_trans: 32,
Expand All @@ -110,7 +114,7 @@
fall_through: false,
},
narrow_xbar_slv_id_width: 4,
narrow_xbar_user_width: 5, // clog2(total number of clusters)
narrow_xbar_user_width: 3, // clog2(total number of clusters)
cfg_base_addr: 184549376, // 0x0b000000
cfg_base_offset: 65536 // 0x10000
},
Expand Down
2 changes: 1 addition & 1 deletion target/sim/sw/device/runtime/src/putchar_chip.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,4 +11,4 @@ void _putchar(char character) {
};

write_reg_u8(UART_THR, character);
}
}
Loading

0 comments on commit 71556ee

Please sign in to comment.