EXT JTAG+UART (#24)

* Update Vivado Scripts * Bug Fix * Bug Fix * Update bd * Update bd
KULeuven-MICAS · Aug 29, 2024 · 65bdf05 · 65bdf05
1 parent e437e2a
commit 65bdf05
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diff --git a/target/fpga_chip/hemaia_system/hemaia_system_vcu128_bd.tcl b/target/fpga_chip/hemaia_system/hemaia_system_vcu128_bd.tcl
@@ -214,8 +214,8 @@ proc create_root_design { parentCell } {
  ] $reset
  set uart_rx_i_0 [ create_bd_port -dir I uart_rx_i_0 ]
  set uart_tx_o_0 [ create_bd_port -dir O uart_tx_o_0 ]
- set jtag_vdd_o [ create_bd_port -dir O -from 0 -to 0 jtag_vdd_o ]
- set jtag_gnd_o [ create_bd_port -dir O -from 0 -to 0 jtag_gnd_o ]
+ set vref_vdd_o [ create_bd_port -dir O -from 0 -to 0 vref_vdd_o ]
+ set vref_gnd_o [ create_bd_port -dir O -from 0 -to 0 vref_gnd_o ]
  set jtag_tdo_o [ create_bd_port -dir O jtag_tdo_o ]
  set jtag_tdi_i [ create_bd_port -dir I jtag_tdi_i ]
  set jtag_tms_i [ create_bd_port -dir I jtag_tms_i ]
@@ -331,10 +331,11 @@ proc create_root_design { parentCell } {
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets Net1]
  connect_bd_net -net Net2 [get_bd_ports i2c_scl_io] [get_bd_pins occamy_chip/i2c_scl_io]
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets Net2]
- connect_bd_net -net c_high_dout [get_bd_pins c_high/dout] [get_bd_ports jtag_vdd_o] [get_bd_pins occamy_chip/jtag_trst_ni]
+ connect_bd_net -net bootmode [get_bd_pins vio_sys/probe_out1] [get_bd_pins occamy_chip/boot_mode_i]
+ connect_bd_net -net c_high_dout [get_bd_pins c_high/dout] [get_bd_ports vref_vdd_o] [get_bd_pins occamy_chip/jtag_trst_ni]
  connect_bd_net -net clk_wiz_clk_core [get_bd_pins clk_wiz/clk_core] [get_bd_pins vio_sys/clk] [get_bd_pins occamy_chip/clk_i] [get_bd_pins occamy_chip/clk_periph_i]
  connect_bd_net -net clk_wiz_clk_rtc [get_bd_pins clk_wiz/clk_rtc] [get_bd_pins occamy_chip/rtc_i]
- connect_bd_net -net const_low_dout [get_bd_pins c_low/dout] [get_bd_ports jtag_gnd_o] [get_bd_pins occamy_chip/test_mode_i] [get_bd_pins occamy_chip/gpio_d_i] [get_bd_pins occamy_chip/ext_irq_i]
+ connect_bd_net -net const_low_dout [get_bd_pins c_low/dout] [get_bd_ports vref_gnd_o] [get_bd_pins occamy_chip/test_mode_i] [get_bd_pins occamy_chip/gpio_d_i] [get_bd_pins occamy_chip/ext_irq_i]
  connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins occamy_chip/jtag_tck_i]
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets jtag_tck_i_1]
  connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins occamy_chip/jtag_tdi_i]
@@ -351,14 +352,13 @@ proc create_root_design { parentCell } {
  connect_bd_net -net occamy_chip_0_uart_tx_o [get_bd_pins occamy_chip/uart_tx_o] [get_bd_ports uart_tx_o_0]
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_uart_tx_o]
  connect_bd_net -net occamy_rst [get_bd_pins rst_or_core/Res] [get_bd_pins rst_core_inv/Op1]
- connect_bd_net -net occamy_rst_vio [get_bd_pins vio_sys/probe_out0] [get_bd_pins concat_rst_core/In1]
  connect_bd_net -net occamy_rstn [get_bd_pins rst_core_inv/Res] [get_bd_pins occamy_chip/rst_ni] [get_bd_pins occamy_chip/rst_periph_ni]
- connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins concat_rst_core/In0]
+ connect_bd_net -net reset [get_bd_pins vio_sys/probe_out0] [get_bd_pins concat_rst_core/In1]
+ connect_bd_net -net reset_button [get_bd_ports reset] [get_bd_pins concat_rst_core/In0]
  connect_bd_net -net uart_cts_ni_0_1 [get_bd_ports uart_cts_ni_0] [get_bd_pins occamy_chip/uart_cts_ni]
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets uart_cts_ni_0_1]
  connect_bd_net -net uart_rx_i_0_1 [get_bd_ports uart_rx_i_0] [get_bd_pins occamy_chip/uart_rx_i]
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets uart_rx_i_0_1]
- connect_bd_net -net vio_sys_probe_out1 [get_bd_pins vio_sys/probe_out1] [get_bd_pins occamy_chip/boot_mode_i]
  connect_bd_net -net xlconcat_2_dout [get_bd_pins concat_rst_core/dout] [get_bd_pins rst_or_core/Op1]
  connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_ports gpio_d_o]
 

diff --git a/target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl.xdc b/target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl.xdc
@@ -5,49 +5,66 @@
 # Nils Wistoff <[email protected]>
 # Yunhao Deng <[email protected]>
 
+# 1 and 0 voltage reference
+# 1: LA20_P - A21
+set_property PACKAGE_PIN A21 [get_ports vref_vdd_o]
+set_property IOSTANDARD LVCMOS15 [get_ports vref_vdd_o]
+set_property DRIVE 12 [get_ports vref_vdd_o]
+
+# 0: LA20_N - A20
+set_property PACKAGE_PIN A20 [get_ports vref_gnd_o]
+set_property IOSTANDARD LVCMOS15 [get_ports vref_gnd_o]
+set_property DRIVE 12 [get_ports vref_gnd_o]
+
 
 # Four-wires UART with flow control
-set_property PACKAGE_PIN BP26 [get_ports uart_rx_i_0]
-set_property IOSTANDARD LVCMOS18 [get_ports uart_rx_i_0]
-set_property PACKAGE_PIN BN26 [get_ports uart_tx_o_0]
-set_property IOSTANDARD LVCMOS18 [get_ports uart_tx_o_0]
-set_property PACKAGE_PIN BP22 [get_ports uart_cts_ni_0]
-set_property IOSTANDARD LVCMOS18 [get_ports uart_cts_ni_0]
-set_property PACKAGE_PIN BP23 [get_ports uart_rts_no_0]
-set_property IOSTANDARD LVCMOS18 [get_ports uart_rts_no_0]
+# LA26P - D17
+set_property PACKAGE_PIN D17 [get_ports uart_rx_i_0]
+set_property IOSTANDARD LVCMOS15 [get_ports uart_rx_i_0]
+# LA26N - D16
+set_property PACKAGE_PIN D16 [get_ports uart_tx_o_0]
+set_property IOSTANDARD LVCMOS15 [get_ports uart_tx_o_0]
+# Flow Control
+# LA27P - E21
+set_property PACKAGE_PIN E21 [get_ports uart_cts_ni_0]
+set_property IOSTANDARD LVCMOS15 [get_ports uart_cts_ni_0]
+set_property PULLUP TRUE [get_ports uart_cts_ni_0]
+# LA27N - D21
+set_property PACKAGE_PIN D21 [get_ports uart_rts_no_0]
+set_property IOSTANDARD LVCMOS15 [get_ports uart_rts_no_0]
 
 # Six-wires SPIx4
-# FMCP_HSPC_LA12_P
-set_property PACKAGE_PIN J22 [get_ports spim_sd_io[0]]
-set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[0]]
-# FMCP_HSPC LA12_N
-set_property PACKAGE_PIN H22 [get_ports spim_sd_io[1]]
-set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[1]]
-# FMCP_HSPC LA16_P
-set_property PACKAGE_PIN K24 [get_ports spim_sd_io[2]]
-set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[2]]
-# FMCP_HSPC_LA16_N
-set_property PACKAGE_PIN K23 [get_ports spim_sd_io[3]]
-set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[3]]
-# FMCP_HSPC_LA20_P
-set_property PACKAGE_PIN A21 [get_ports spim_csb_o[0]]
-set_property IOSTANDARD LVCMOS18 [get_ports spim_csb_o[0]]
-# FMCP_HSPC_LA20_N
-set_property PACKAGE_PIN A20 [get_ports spim_csb_o[1]]
-set_property IOSTANDARD LVCMOS18 [get_ports spim_csb_o[1]]
-# FMCP_HSPC_LA22_P
-set_property PACKAGE_PIN B16 [get_ports spim_sck_o]
-set_property IOSTANDARD LVCMOS18 [get_ports spim_sck_o]
+# LA10_P - B23
+set_property PACKAGE_PIN B23 [get_ports spim_sd_io[0]]
+set_property IOSTANDARD LVCMOS15 [get_ports spim_sd_io[0]]
+# LA10_N - A23
+set_property PACKAGE_PIN A23 [get_ports spim_sd_io[1]]
+set_property IOSTANDARD LVCMOS15 [get_ports spim_sd_io[1]]
+# LA11_P - B26
+set_property PACKAGE_PIN B26 [get_ports spim_sd_io[2]]
+set_property IOSTANDARD LVCMOS15 [get_ports spim_sd_io[2]]
+# LA11_N - B25
+set_property PACKAGE_PIN B25 [get_ports spim_sd_io[3]]
+set_property IOSTANDARD LVCMOS15 [get_ports spim_sd_io[3]]
+# LA12_P - J22
+set_property PACKAGE_PIN J22 [get_ports spim_csb_o[0]]
+set_property IOSTANDARD LVCMOS15 [get_ports spim_csb_o[0]]
+# LA12_N - H22
+set_property PACKAGE_PIN H22 [get_ports spim_csb_o[1]]
+set_property IOSTANDARD LVCMOS15 [get_ports spim_csb_o[1]]
+# LA13_P - A25
+set_property PACKAGE_PIN A25 [get_ports spim_sck_o]
+set_property IOSTANDARD LVCMOS15 [get_ports spim_sck_o]
 
 create_clock -period 10.000 -name spi_m_sck [get_ports spim_sck_o]
 
 # Two-wires I2C
-# FMCP_HSPC_LA13_P
-set_property PACKAGE_PIN A25 [get_ports i2c_sda_io]
-set_property IOSTANDARD LVCMOS18 [get_ports i2c_sda_io]
-# FMCP_HSPC_LA13_N
-set_property PACKAGE_PIN A24 [get_ports i2c_scl_io]
-set_property IOSTANDARD LVCMOS18 [get_ports i2c_scl_io]
+# LA14_P - C23
+set_property PACKAGE_PIN C23 [get_ports i2c_sda_io]
+set_property IOSTANDARD LVCMOS15 [get_ports i2c_sda_io]
+# LA14_N - B22
+set_property PACKAGE_PIN B22 [get_ports i2c_scl_io]
+set_property IOSTANDARD LVCMOS15 [get_ports i2c_scl_io]
 
 # Eight-wires GPIO_O connected to LEDs
 set_property PACKAGE_PIN BH24 [get_ports gpio_d_o[0]]

diff --git a/target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl_ext_jtag.xdc b/target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl_ext_jtag.xdc
@@ -24,21 +24,15 @@ set_max_delay -to [get_ports { jtag_tdo_o }] 20
 set_max_delay -from [get_ports { jtag_tms_i }] 20
 set_max_delay -from [get_ports { jtag_tdi_i }] 20
 
-# C23 - C18 (FMCP_HSPC_LA14_P) - J1.02 - VDD
-set_property PACKAGE_PIN C23 [get_ports jtag_vdd_o]
-set_property IOSTANDARD LVCMOS18 [get_ports jtag_vdd_o]
-# B22 - C19 (FMCP_HSPC_LA14_N) - J1.04 - GND
-set_property PACKAGE_PIN B22 [get_ports jtag_gnd_o]
-set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o]
-# E19 - C22 (FMCP_HSPC_LA18_CC_P) - J1.06 - TCK
-set_property PACKAGE_PIN E19 [get_ports jtag_tck_i]
-set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i]
-# E18 - C23 (FMCP_HSPC_LA19_CC_N) - J1.08 - TDO
-set_property PACKAGE_PIN E18 [get_ports jtag_tdo_o]
-set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o]
-# E21 - C26 (FMCP_HSPC_LA27_P) - J1.10 - TDI
-set_property PACKAGE_PIN E21 [get_ports jtag_tdi_i]
-set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i]
-# D21 - C27 (FMCP_HSPC_LA27_N) - J1.12 - TNS
-set_property PACKAGE_PIN D21 [get_ports jtag_tms_i]
-set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i]
+# LA24P - C18
+set_property PACKAGE_PIN C18 [get_ports jtag_tck_i]
+set_property IOSTANDARD LVCMOS15 [get_ports jtag_tck_i]
+# LA24N - C17
+set_property PACKAGE_PIN C17 [get_ports jtag_tdi_i]
+set_property IOSTANDARD LVCMOS15 [get_ports jtag_tdi_i]
+# LA25P - D20
+set_property PACKAGE_PIN D20 [get_ports jtag_tdo_o]
+set_property IOSTANDARD LVCMOS15 [get_ports jtag_tdo_o]
+# LA25N - D19
+set_property PACKAGE_PIN D19 [get_ports jtag_tms_i]
+set_property IOSTANDARD LVCMOS15 [get_ports jtag_tms_i]
diff --git a/target/fpga_chip/hemaia_system/hemaia_system_vpk180_bd.tcl b/target/fpga_chip/hemaia_system/hemaia_system_vpk180_bd.tcl
@@ -209,8 +209,8 @@ proc create_root_design { parentCell } {
  ] $reset
  set uart_rx_i_0 [ create_bd_port -dir I uart_rx_i_0 ]
  set uart_tx_o_0 [ create_bd_port -dir O uart_tx_o_0 ]
- set jtag_vdd_o [ create_bd_port -dir O -from 0 -to 0 jtag_vdd_o ]
- set jtag_gnd_o [ create_bd_port -dir O -from 0 -to 0 jtag_gnd_o ]
+ set vref_vdd_o [ create_bd_port -dir O -from 0 -to 0 vref_vdd_o ]
+ set vref_gnd_o [ create_bd_port -dir O -from 0 -to 0 vref_gnd_o ]
  set jtag_tdo_o [ create_bd_port -dir O jtag_tdo_o ]
  set jtag_tdi_i [ create_bd_port -dir I jtag_tdi_i ]
  set jtag_tms_i [ create_bd_port -dir I jtag_tms_i ]
@@ -340,11 +340,10 @@ proc create_root_design { parentCell } {
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets Net1]
  connect_bd_net -net Net2 [get_bd_ports i2c_scl_io] [get_bd_pins occamy_chip/i2c_scl_io]
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets Net2]
- connect_bd_net -net axis_vio_0_probe_out0 [get_bd_pins axis_vio_0/probe_out0] [get_bd_pins concat_rst_core/In1]
- connect_bd_net -net axis_vio_0_probe_out1 [get_bd_pins axis_vio_0/probe_out1] [get_bd_pins occamy_chip/boot_mode_i]
- connect_bd_net -net c_high_dout [get_bd_pins c_high/dout] [get_bd_ports jtag_vdd_o] [get_bd_pins occamy_chip/jtag_trst_ni]
+ connect_bd_net -net bootmode [get_bd_pins axis_vio_0/probe_out1] [get_bd_pins occamy_chip/boot_mode_i]
+ connect_bd_net -net c_high_dout [get_bd_pins c_high/dout] [get_bd_ports vref_vdd_o] [get_bd_pins occamy_chip/jtag_trst_ni]
  connect_bd_net -net clk_wizard_0_clk_core [get_bd_pins versal_cips_0/pl0_ref_clk] [get_bd_pins axis_vio_0/clk] [get_bd_pins occamy_chip/clk_i] [get_bd_pins occamy_chip/clk_periph_i]
- connect_bd_net -net const_low_dout [get_bd_pins c_low/dout] [get_bd_ports jtag_gnd_o] [get_bd_pins occamy_chip/test_mode_i] [get_bd_pins occamy_chip/gpio_d_i] [get_bd_pins occamy_chip/ext_irq_i]
+ connect_bd_net -net const_low_dout [get_bd_pins c_low/dout] [get_bd_ports vref_gnd_o] [get_bd_pins occamy_chip/test_mode_i] [get_bd_pins occamy_chip/gpio_d_i] [get_bd_pins occamy_chip/ext_irq_i]
  connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins occamy_chip/jtag_tck_i]
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets jtag_tck_i_1]
  connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins occamy_chip/jtag_tdi_i]
@@ -362,7 +361,8 @@ proc create_root_design { parentCell } {
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_uart_tx_o]
  connect_bd_net -net occamy_rst [get_bd_pins rst_or_core/Res] [get_bd_pins rst_core_inv/Op1]
  connect_bd_net -net occamy_rstn [get_bd_pins rst_core_inv/Res] [get_bd_pins occamy_chip/rst_ni] [get_bd_pins occamy_chip/rst_periph_ni]
- connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins concat_rst_core/In0]
+ connect_bd_net -net reset [get_bd_pins axis_vio_0/probe_out0] [get_bd_pins concat_rst_core/In1]
+ connect_bd_net -net reset_button [get_bd_ports reset] [get_bd_pins concat_rst_core/In0]
  connect_bd_net -net uart_cts_ni_0_1 [get_bd_ports uart_cts_ni_0] [get_bd_pins occamy_chip/uart_cts_ni]
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets uart_cts_ni_0_1]
  connect_bd_net -net uart_rx_i_0_1 [get_bd_ports uart_rx_i_0] [get_bd_pins occamy_chip/uart_rx_i]

diff --git a/target/fpga_chip/hemaia_system/hemaia_system_vpk180_impl.xdc b/target/fpga_chip/hemaia_system/hemaia_system_vpk180_impl.xdc
@@ -5,63 +5,73 @@
 # Nils Wistoff <[email protected]>
 # Yunhao Deng <[email protected]>
 
+# 1 and 0 voltage reference
+# 1: LA20_P - BR42
+set_property PACKAGE_PIN BR42 [get_ports vref_vdd_o]
+set_property IOSTANDARD LVCMOS15 [get_ports vref_vdd_o]
+set_property DRIVE 12 [get_ports vref_vdd_o]
+
+# 0: LA20_N - BT41
+set_property PACKAGE_PIN BT41 [get_ports vref_gnd_o]
+set_property IOSTANDARD LVCMOS15 [get_ports vref_gnd_o]
+set_property DRIVE 12 [get_ports vref_gnd_o]
 
 # Four-wires UART with flow control
-set_property PACKAGE_PIN AY44 [get_ports uart_rx_i_0]
-set_property IOSTANDARD LVCMOS15 [get_ports uart_rx_i_0]
-set_property PACKAGE_PIN AW44 [get_ports uart_tx_o_0]
-set_property IOSTANDARD LVCMOS15 [get_ports uart_tx_o_0]
+# set_property PACKAGE_PIN AY44 [get_ports uart_rx_i_0]
+# set_property IOSTANDARD LVCMOS15 [get_ports uart_rx_i_0]
+# set_property PACKAGE_PIN AW44 [get_ports uart_tx_o_0]
+# set_property IOSTANDARD LVCMOS15 [get_ports uart_tx_o_0]
 # FT4232HL's flow control is not connected to the FPGA... 
 # The external UART alternative
 # Data
-# # LA25P - CC38
-# set_property PACKAGE_PIN CC38 [get_ports uart_rx_i_0]
-# set_property IOSTANDARD LVCMOS15 [get_ports uart_rx_i_0]
-# # LA25N - CC39
-# set_property PACKAGE_PIN CC39 [get_ports uart_tx_o_0]
-# set_property IOSTANDARD LVCMOS15 [get_ports uart_tx_o_0]
+# LA26P - CB41
+set_property PACKAGE_PIN CB41 [get_ports uart_rx_i_0]
+set_property IOSTANDARD LVCMOS15 [get_ports uart_rx_i_0]
+# LA26N - CC42
+set_property PACKAGE_PIN CC42 [get_ports uart_tx_o_0]
+set_property IOSTANDARD LVCMOS15 [get_ports uart_tx_o_0]
 # Flow Control
-# LA29P - BY38
-set_property PACKAGE_PIN BY38 [get_ports uart_cts_ni_0]
+# LA27P - CA38
+set_property PACKAGE_PIN CA38 [get_ports uart_cts_ni_0]
 set_property IOSTANDARD LVCMOS15 [get_ports uart_cts_ni_0]
-set_property PULLDOWN TRUE [get_ports uart_cts_ni_0]
-# LA29N - CA37
-set_property PACKAGE_PIN CA37 [get_ports uart_rts_no_0]
+set_property PULLUP TRUE [get_ports uart_cts_ni_0]
+# LA27N - CB39
+set_property PACKAGE_PIN CB39 [get_ports uart_rts_no_0]
 set_property IOSTANDARD LVCMOS15 [get_ports uart_rts_no_0]
 
 # Six-wires SPIx4
-# FMCP_HSPC_LA12_P
-set_property PACKAGE_PIN BW49 [get_ports spim_sd_io[0]]
+# FMCP_HSPC_LA10_P
+set_property PACKAGE_PIN CC44 [get_ports spim_sd_io[0]]
 set_property IOSTANDARD LVCMOS15 [get_ports spim_sd_io[0]]
-# FMCP_HSPC LA12_N
-set_property PACKAGE_PIN BW50 [get_ports spim_sd_io[1]]
+# FMCP_HSPC LA10_N
+set_property PACKAGE_PIN CD45 [get_ports spim_sd_io[1]]
 set_property IOSTANDARD LVCMOS15 [get_ports spim_sd_io[1]]
-# FMCP_HSPC LA16_P
-set_property PACKAGE_PIN CA51 [get_ports spim_sd_io[2]]
+# FMCP_HSPC LA11_P
+set_property PACKAGE_PIN CB51 [get_ports spim_sd_io[2]]
 set_property IOSTANDARD LVCMOS15 [get_ports spim_sd_io[2]]
-# FMCP_HSPC_LA16_N
-set_property PACKAGE_PIN CB52 [get_ports spim_sd_io[3]]
+# FMCP_HSPC_LA11_N
+set_property PACKAGE_PIN CC52 [get_ports spim_sd_io[3]]
 set_property IOSTANDARD LVCMOS15 [get_ports spim_sd_io[3]]
-# FMCP_HSPC_LA20_P
-set_property PACKAGE_PIN BR42 [get_ports spim_csb_o[0]]
+# FMCP_HSPC_LA12_P
+set_property PACKAGE_PIN BW49 [get_ports spim_csb_o[0]]
 set_property IOSTANDARD LVCMOS15 [get_ports spim_csb_o[0]]
-# FMCP_HSPC_LA20_N
-set_property PACKAGE_PIN BT41 [get_ports spim_csb_o[1]]
+# FMCP_HSPC_LA12_N
+set_property PACKAGE_PIN BW50 [get_ports spim_csb_o[1]]
 set_property IOSTANDARD LVCMOS15 [get_ports spim_csb_o[1]]
-# FMCP_HSPC_LA22_P
-set_property PACKAGE_PIN CD42 [get_ports spim_sck_o]
+# FMCP_HSPC_LA13_P
+set_property PACKAGE_PIN CC49 [get_ports spim_sck_o]
 set_property IOSTANDARD LVCMOS15 [get_ports spim_sck_o]
 
 create_clock -period 10.000 -name spi_m_sck [get_ports spim_sck_o]
 
 # Two-wires I2C
-# FMCP_HSPC_LA13_P
-set_property PACKAGE_PIN CC49 [get_ports i2c_sda_io]
+# FMCP_HSPC_LA14_P
+set_property PACKAGE_PIN BY51 [get_ports i2c_sda_io]
 set_property IOSTANDARD LVCMOS15 [get_ports i2c_sda_io]
 set_property PULLUP TRUE [get_ports i2c_sda_io]
 
-# FMCP_HSPC_LA13_N
-set_property PACKAGE_PIN CD50 [get_ports i2c_scl_io]
+# FMCP_HSPC_LA14_N
+set_property PACKAGE_PIN CA52 [get_ports i2c_scl_io]
 set_property IOSTANDARD LVCMOS15 [get_ports i2c_scl_io]
 set_property PULLUP TRUE [get_ports i2c_scl_io]
 

diff --git a/target/fpga_chip/hemaia_system/hemaia_system_vpk180_impl_ext_jtag.xdc b/target/fpga_chip/hemaia_system/hemaia_system_vpk180_impl_ext_jtag.xdc
@@ -24,21 +24,15 @@ set_max_delay -to [get_ports { jtag_tdo_o }] 20
 set_max_delay -from [get_ports { jtag_tms_i }] 20
 set_max_delay -from [get_ports { jtag_tdi_i }] 20
 
-# C23 - C18 (FMCP_HSPC_LA14_P) - J1.02 - VDD
-set_property PACKAGE_PIN BY51 [get_ports jtag_vdd_o]
-set_property IOSTANDARD LVCMOS15 [get_ports jtag_vdd_o]
-# B22 - C19 (FMCP_HSPC_LA14_N) - J1.04 - GND
-set_property PACKAGE_PIN CA52 [get_ports jtag_gnd_o]
-set_property IOSTANDARD LVCMOS15 [get_ports jtag_gnd_o]
-# E19 - C22 (FMCP_HSPC_LA18_CC_P) - J1.06 - TCK
-set_property PACKAGE_PIN BW39 [get_ports jtag_tck_i]
+# LA24P - BY40
+set_property PACKAGE_PIN BY40 [get_ports jtag_tck_i]
 set_property IOSTANDARD LVCMOS15 [get_ports jtag_tck_i]
-# E18 - C23 (FMCP_HSPC_LA19_CC_N) - J1.08 - TDO
-set_property PACKAGE_PIN BP40 [get_ports jtag_tdo_o]
-set_property IOSTANDARD LVCMOS15 [get_ports jtag_tdo_o]
-# E21 - C26 (FMCP_HSPC_LA27_P) - J1.10 - TDI
-set_property PACKAGE_PIN CA38 [get_ports jtag_tdi_i]
+# LA24N - CA39
+set_property PACKAGE_PIN CA39 [get_ports jtag_tdi_i]
 set_property IOSTANDARD LVCMOS15 [get_ports jtag_tdi_i]
-# D21 - C27 (FMCP_HSPC_LA27_N) - J1.12 - TNS
-set_property PACKAGE_PIN CA39 [get_ports jtag_tms_i]
+# LA25P - CC38
+set_property PACKAGE_PIN CC38 [get_ports jtag_tdo_o]
+set_property IOSTANDARD LVCMOS15 [get_ports jtag_tdo_o]
+# LA25N - CC39
+set_property PACKAGE_PIN CC39 [get_ports jtag_tms_i]
 set_property IOSTANDARD LVCMOS15 [get_ports jtag_tms_i]