arch/xtensa: Add automatic vector linkage generation #72771
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Some more automitization[1] of a particularly ugly area of Xtensa platform integration. There's a really shocking amount of manually customized linker script nonsense on these platforms, and it's all needless as the offsets involved are specified in core-isa.h. As elsewhere, only dc233c is enabled for a start. Platform owners can manage the transition at leisure. [1] Edit: automITization? Weird typo. Almost seems like it should be a real word. |
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(Fix pylint squawks) |
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Review ping. This is split out from the mt8195 PR but can merge separately. |
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Looks like this still needs one more approval, Xtensa linkage is admittedly obscure and Daniel and I are the only regulars who touch it at the arch level: @dbaluta @iuliana-prodan @sylvioalves @marekmatej are Xtensa experts too though. :) |
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Oh, heh, and a rebase. One sec. |
Existing solutions for linking the Xtensa vector table are a
cut-and-paste mess of inherited code, with more than a dozen special
sections that need to be linked into many special MEMORY{} regions.
Accept the existing convention used by C/asm code, but automatically
detect the needed offsets for the platform from core-isa.h (it can
share the preprocessing with gen_zsr.py) and emit a file that can be
included in lieu of all the existing boilerplate.
Signed-off-by: Andy Ross <[email protected]>
Remove all the hard-configured absolute addresses and zillions of tiny ELF segments in favor of the auto-generated vector region, which is guaranteed correct as long as core-isa.h is matched to the target. Signed-off-by: Andy Ross <[email protected]>
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Existing solutions for linking the Xtensa vector table are a cut-and-paste mess of inherited code, with more than a dozen special sections that need to be linked into many special MEMORY{} regions.
Accept the existing convention used by C/asm code, but automatically detect the needed offsets for the platform from core-isa.h (it can share the preprocessing with gen_zsr.py) and emit a file that can be included in lieu of all the existing boilerplate.