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arch/xtensa: Automatically generate interrupt handlers (finally) #72768

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merged 4 commits into from
May 21, 2024

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andyross
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The script to generate the _soc_inthandlers.h header has been run manually for years, only because I was a cmake novice at the time and unsure how to integrate it into the build. So every new platform has to find the script and template file and figure out how to generate the file. And in a few cases it looks like we've tried to EDIT the resulting files in the tree.

Let's finally do this right. The file is now dropped (for every xtensa platform) as a "xtensa_handlers.h" file, and there is a Kconfig to control whether the original/manual file or the new one is used by the platform code. We can migrate the other platforms slowly as people have time to validate.

The script to generate the _soc_inthandlers.h header has been run
manually for years, only because I was a cmake novice at the time and
unsure how to integrate it into the build.  So every new platform has
to find the script and template file and figure out how to generate
the file.  And in a few cases it looks like we've tried to EDIT the
resulting files in the tree.

Let's finally do this right.  The file is now dropped (for every
xtensa platform) as a "xtensa_handlers.h" file, and there is a Kconfig
to control whether the original/manual file or the new one is used by
the platform code.  We can migrate the other platforms slowly as
people have time to validate.

Signed-off-by: Andy Ross <[email protected]>
Some oddballs cores can be generated without an "NMI" interrupt, in
which case core-isa.h will not define XCHAL_NMILEVEL.  This code is
trying to unconditionally mask interrupts, so XCHAL_EXCM_LEVEL is the
pedantically correct choice anyway (NMI's by definition, cannot be
masked).

Signed-off-by: Andy Ross <[email protected]>
The original code would (unsurprisingly) only emit handler functions
for interrupt levels with interrupts associated with them.  But it
turns out that it's possible to configure an xtensa device with an
empty-but-otherwise-real interrupt level (specifically mt8195 has a
"Level 3" interrupt not associated with any input IRQS, it's one level
above EXCM_LEVEL and one level below the DEBUG exception).

This script is old, and not set up to parse the full core-isa.h
directly, so modifying it to detect this condition is difficult.
Instead, just emit all 15 possible interrupt handlers, even empty
ones.  The extra stubs are harmless as they'll be dropped if uncalled.

Signed-off-by: Andy Ross <[email protected]>
@andyross andyross requested review from ceolin and dcpleung May 14, 2024 20:18
@zephyrbot zephyrbot added the area: Xtensa Xtensa Architecture label May 14, 2024
@zephyrbot zephyrbot requested a review from nashif May 14, 2024 20:18
@andyross
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I include the integration for dc233c only as that's all I can smoke test easily. Other platforms can set the kconfig and remove their own _soc_inthandlers.h at leisure.

The script runs as part of the build now.  Use that feature and
remove the old static file from the manually-run script.

Signed-off-by: Andy Ross <[email protected]>
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Review and tested on imx8mp_evk//adsp, imx8qm_mek//adsp, imx8qxp_mek//adsp.

@andyross
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Quick ping for review. @dcpleung and @ceolin in particular want to look at this.

@nashif nashif merged commit 1472195 into zephyrproject-rtos:main May 21, 2024
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5 participants