drivers: watchdog: NXP: Fix WDG option handling #72753
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| @@ -42,10 +42,10 @@ static int mcux_wdog_setup(const struct device *dev, uint8_t options) | |||
| } | |||
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| data->wdog_config.workMode.enableStop = | |||
| (options & WDT_OPT_PAUSE_IN_SLEEP) == 0U; | |||
| (options & WDT_OPT_PAUSE_IN_SLEEP) == WDT_OPT_PAUSE_IN_SLEEP; | |||
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The WDT_OPT_PAUSE_IN_SLEEP bit is documented as follows:
Pause watchdog timer when CPU is in sleep state
Therefore, if the bit is cleared, then the watchdog should run in sleep mode, correct?
For the iMX WDOG, Setting enableStop results in the WDZST bit being cleared, so the timer will run in low power modes.
From my understanding of the documentation and the iMX WDOG IP, the current behavior would be correct- is there something I'm missing here?
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I run into the issue on a IMXRT1064 where the watchdog was running during debug halt although WDT_OPT_PAUSE_HALTED_BY_DBG was set. Inverting the logic fixed the issue.
Digging deeper into the RM I found that the logic is different for WDOG and RTWDOG:
WDOG_WCR_WDBG: 1b - Suspend the watchdog timer.
RTWDOG_CS_DBG: 1b - Watchdog enabled in chip debug mode.
(from IMXRT1064 reference manual)
This is already fixed in the HAL update to SDK 2.15.000
https://github.com/zephyrproject-rtos/hal_nxp/blame/7da0fc961f861b011b7f68a5085d29ee2b401957/mcux/mcux-sdk/drivers/wdog01/fsl_wdog.c#L111-L112
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please change commit title to begin with drivers: wdt_mcux_imx: , as there are multiple nxp watchdogs in the tree |
If `enableStop` is true the watchdog is halted in chip stop mode. If `enableDebug` is true the watchdog is halted in chip debug mode. Signed-off-by: David Schneider <[email protected]>
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The logic in the Zephyr driver is correct and the the issue I faced get resolved with the latest HAL update. |
If
enableStopis true the watchdog is halted in chip stop mode.If
enableDebugis true the watchdog is halted in chip debug mode.