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@xlsynth

xlsynth

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  1. bedrock-rtl bedrock-rtl Public

    High quality and composable RTL libraries in SystemVerilog

    SystemVerilog 19 3

  2. dslx-vscode dslx-vscode Public

    Forked from kammoh/dslx-vscode

    XLS DSLX Language Support for Visual Studio Code

    TypeScript 4

  3. topstitch topstitch Public

    Stitch together Verilog modules with Rust

    Rust 4

  4. xlsynth xlsynth Public

    Forked from google/xls

    XLSynth: Accelerated HW Synthesis

    C++ 3 1

  5. slang-rs slang-rs Public

    Rust bindings for the Slang Verilog parser

    Rust 2 2

  6. dslx-llm dslx-llm Public

    Collateral for working on "DSLX", the DSL from XLS, via LLMs

    Python 1

Repositories

Showing 10 of 14 repositories
  • xlsynth-crate Public

    Rust crate that publishes XLSynth capabilities (wrapping libxlsynth.so/.dylib)

    xlsynth/xlsynth-crate’s past year of commit activity
    Rust 0 Apache-2.0 2 6 0 Updated Apr 14, 2025
  • topstitch Public

    Stitch together Verilog modules with Rust

    xlsynth/topstitch’s past year of commit activity
    Rust 4 Apache-2.0 0 9 1 Updated Apr 14, 2025
  • slang-rs Public

    Rust bindings for the Slang Verilog parser

    xlsynth/slang-rs’s past year of commit activity
    Rust 2 Apache-2.0 2 1 1 Updated Apr 14, 2025
  • bedrock-rtl Public

    High quality and composable RTL libraries in SystemVerilog

    xlsynth/bedrock-rtl’s past year of commit activity
    SystemVerilog 19 Apache-2.0 3 13 10 Updated Apr 14, 2025
  • rules_xlsynth Public

    "Next-Generation" Bazel Rules for DSLX and XLS/XLSynth based projects

    xlsynth/rules_xlsynth’s past year of commit activity
    Starlark 0 Apache-2.0 0 1 0 Updated Apr 11, 2025
  • xlsynth Public Forked from google/xls

    XLSynth: Accelerated HW Synthesis

    xlsynth/xlsynth’s past year of commit activity
    C++ 3 Apache-2.0 205 0 1 Updated Apr 11, 2025
  • xls-pr-data Public

    Data for PRs to the XLS repo

    xlsynth/xls-pr-data’s past year of commit activity
    Python 1 Apache-2.0 0 0 0 Updated Apr 11, 2025
  • dslx-llm Public

    Collateral for working on "DSLX", the DSL from XLS, via LLMs

    xlsynth/dslx-llm’s past year of commit activity
    Python 1 Apache-2.0 0 1 0 Updated Apr 1, 2025
  • pulp_axi Public Forked from pulp-platform/axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    xlsynth/pulp_axi’s past year of commit activity
    SystemVerilog 0 289 0 0 Updated Mar 25, 2025
  • pulp_common_cells Public Forked from pulp-platform/common_cells

    Common SystemVerilog components

    xlsynth/pulp_common_cells’s past year of commit activity
    SystemVerilog 0 160 0 0 Updated Mar 24, 2025
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