Improve DEFSERCFG Config

- Move DEFSERCFG from an equate to a #DEFINE which allows properly overriding it globally.
wwarthen · Jan 19, 2025 · ab4f43c · ab4f43c
1 parent e4bbeec
commit ab4f43c
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diff --git a/Doc/RomWBW Applications.pdf b/Doc/RomWBW Applications.pdf
diff --git a/Doc/RomWBW Disk Catalog.pdf b/Doc/RomWBW Disk Catalog.pdf
diff --git a/Doc/RomWBW Errata.pdf b/Doc/RomWBW Errata.pdf
diff --git a/Doc/RomWBW System Guide.pdf b/Doc/RomWBW System Guide.pdf
diff --git a/Doc/RomWBW User Guide.pdf b/Doc/RomWBW User Guide.pdf
diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md
@@ -0,0 +1,29 @@
+This file contains information useful to those upgrading to a new
+release of RomWBW.
+
+All Versions
+============
+
+- Please review Section "15 Upgrading" of the RomWBW User Guide.
+
+- Many RomWBW-specific applications are locked to the ROM version
+  being used.  After upgrading your ROM, you will need to upgrade
+  your disk-based RomWBW applications and OS boot files.
+
+Version 3.5
+===========
+
+- RomWBW is now more strict with respect to hard disk partition
+  tables.  If your hard disk media was created using any of the
+  pre-built disk image files, this will **not** affect you.  If not,
+  you may find you are unable to access slices beyond the first
+  slice.  If so, use FDISK80 to reset the partition table on the
+  disk.  This will restore normal access to all slices.  **Only** do
+  this if you are having an issue.
+
+- For those building custom ROMs, if you overriding
+  DEFSERCFG, note that this setting has been moved to a #DEFINE
+  instead of an equate (.SET or .EQU).  See cfg_MASTER.asm for
+  an example.  You will need to change your setting to a #DEFINE
+  at the top of your config file and remove any .SET or .EQU
+  lines for DEFSERCFG.
diff --git a/ReadMe.md b/ReadMe.md
@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.5 \
 Wayne Warthen  ([[email protected]](mailto:[email protected])) \
-05 Jan 2025
+18 Jan 2025
 
 # Overview
 
@@ -113,6 +113,9 @@ functionality.
 Complete instructions for installation and operation of RomWBW are found
 in the [RomWBW User
 Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20User%20Guide.pdf).
+It is also a good idea to review the [Release
+Notes](https://github.com/wwarthen/RomWBW/blob/master/RELEASE_NOTES.md)
+for helpful release-specific information.
 
 ## Documentation
 

diff --git a/ReadMe.txt b/ReadMe.txt
@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen ([email protected])
-05 Jan 2025
+18 Jan 2025
 
 
 
@@ -112,7 +112,8 @@ drives (IDE disk, CF Card, SD Card, etc.) which then provides even more
 functionality.
 
 Complete instructions for installation and operation of RomWBW are found
-in the RomWBW User Guide.
+in the RomWBW User Guide. It is also a good idea to review the Release
+Notes for helpful release-specific information.
 
 
 Documentation

diff --git a/Source/Doc/ReadMe.md b/Source/Doc/ReadMe.md
@@ -105,7 +105,9 @@ drives (IDE disk, CF Card, SD Card, etc.) which then provides even more
 functionality.
 
 Complete instructions for installation and operation of RomWBW are
-found in the $doc_user$.
+found in the $doc_user$.  It is also a good idea to review the
+[Release Notes](https://github.com/wwarthen/RomWBW/blob/master/RELEASE_NOTES.md)
+for helpful release-specific information.
 
 ## Documentation
 
@@ -192,7 +194,7 @@ please let me know if I missed you!
 * Mark Pruden has also contributed a great deal of content to the
   Disk Catalog, User Guide as well as contributing the disk image
   for the Z3PLUS operating system, the COPYSL utility, and also
-  implemented a feature for RomWBW configuration by NVRAM, 
+  implemented a feature for RomWBW configuration by NVRAM,
   and added the /B bulk mode of disk assignment to the ASSIGN utility.
 
 * Jacques Pelletier has contributed the DS1501 RTC driver code.

diff --git a/Source/HBIOS/cfg_DUO.asm b/Source/HBIOS/cfg_DUO.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Duodyne", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_38400_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -63,7 +64,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_UNSUP	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_DYNO.asm b/Source/HBIOS/cfg_DYNO.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Dyno", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_38400_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +63,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_EPITX.asm b/Source/HBIOS/cfg_EPITX.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "MiniITX"
+#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +63,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_FZ80.asm b/Source/HBIOS/cfg_FZ80.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "S100 FPGA Z80", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +63,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_GMZ180.asm b/Source/HBIOS/cfg_GMZ180.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +63,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_HEATH.asm b/Source/HBIOS/cfg_HEATH.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "HEATHKIT", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +63,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	16384000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_MASTER.asm b/Source/HBIOS/cfg_MASTER.asm
@@ -43,6 +43,7 @@
 ; TO REDEFINE A PREVIOUS DEFINITION.
 ;
 #DEFINE PLATFORM_NAME "RomWBW", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_9600_8N1
 ;
 #INCLUDE "hbios.inc"
 ;
@@ -64,7 +65,7 @@ CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	1000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_9600_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.EQU	SER_9600_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_MBC.asm b/Source/HBIOS/cfg_MBC.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Nhyodyne", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_38400_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -63,7 +64,7 @@ CPUSPDCAP	.SET	SPD_HILO	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_LOW		; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_MK4.asm b/Source/HBIOS/cfg_MK4.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Mark IV", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_38400_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +63,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_MON.asm b/Source/HBIOS/cfg_MON.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Monsputer", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +63,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	4000000		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_N8.asm b/Source/HBIOS/cfg_N8.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "RetroBrew N8", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_38400_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +63,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_NABU.asm b/Source/HBIOS/cfg_NABU.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "NABU Personal Computer", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_38400_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +63,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	3580000		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_RCEZ80.asm b/Source/HBIOS/cfg_RCEZ80.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +63,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	20000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_RCZ180.asm b/Source/HBIOS/cfg_RCZ180.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +63,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_RCZ280.asm b/Source/HBIOS/cfg_RCZ280.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +63,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_RCZ80.asm b/Source/HBIOS/cfg_RCZ80.asm
@@ -43,6 +43,8 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS
+#DEFINE DEFSERCFG xxxxx
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +64,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;;;;DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_RPH.asm b/Source/HBIOS/cfg_RPH.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Rhyophyre", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_38400_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +63,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)

diff --git a/Source/HBIOS/cfg_S100.asm b/Source/HBIOS/cfg_S100.asm
@@ -43,6 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "S100", " [", CONFIG, "]"
+#DEFINE DEFSERCFG SER_57600_8N1 | SER_RTS
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -62,7 +63,7 @@ CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.SET	SER_57600_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;;;DEFSERCFG	.SET	SER_57600_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)