Missing Config & Add Doc

- Add missing config file for K80W - Add K80W to documentation
wwarthen · Dec 31, 2024 · 63460a9 · 63460a9
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diff --git a/Doc/RomWBW Applications.pdf b/Doc/RomWBW Applications.pdf
diff --git a/Doc/RomWBW Disk Catalog.pdf b/Doc/RomWBW Disk Catalog.pdf
diff --git a/Doc/RomWBW Errata.pdf b/Doc/RomWBW Errata.pdf
diff --git a/Doc/RomWBW System Guide.pdf b/Doc/RomWBW System Guide.pdf
diff --git a/Doc/RomWBW User Guide.pdf b/Doc/RomWBW User Guide.pdf
diff --git a/ReadMe.md b/ReadMe.md
@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.5 \
 Wayne Warthen  ([[email protected]](mailto:[email protected])) \
-22 Dec 2024
+31 Dec 2024
 
 # Overview
 

diff --git a/ReadMe.txt b/ReadMe.txt
@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen ([email protected])
-22 Dec 2024
+31 Dec 2024
 
 
 

diff --git a/Source/Doc/UserGuide.md b/Source/Doc/UserGuide.md
@@ -253,6 +253,7 @@ is discussed in [Customizing RomWBW].
 | [Z80 ZRC CPU Module]^7^ ROMless                             | RCBus   | RCZ80_zrc_ram_std.rom        | 115200        |
 | [Z80 ZRC512 CPU Module]^7^                                  | RCBus   | RCZ80_zrc512_std.rom         | 115200        |
 | [Z80 EaZy80-512 CPU Module]^7^                              | RCBus   | RCZ80_ez512_std.rom          | 115200        |
+| [Z80 K80W CPU Module]^7^                                    | RCBus   | RCZ80_k8w_std.rom            | 115200        |
 | [Z180 Z1RCC CPU Module]^7^                                  | RCBus   | RCZ180_z1rcc_std.rom         | 115200        |
 | [Z280 ZZRCC CPU Module]^7^                                  | RCBus   | RCZ280_zzrcc_std.rom         | 115200        |
 | [Z280 ZZRCC CPU Module]^7^ ROMless                          | RCBus   | RCZ280_zzrcc_ram_std.rom     | 115200        |
@@ -6168,6 +6169,51 @@ the RomWBW HBIOS configuration.
 
 `\clearpage`{=latex}
 
+#### ROM Image File:  RCZ80_k8w_std.rom
+
+|                   |               |
+|-------------------|---------------|
+| Default CPU Speed | 22.000 MHz    |
+| Interrupts        | Mode 2        |
+| System Timer      | CTC           |
+| Serial Default    | 115200 Baud   |
+| Memory Manager    | Z2            |
+| ROM Size          | 512 KB        |
+| RAM Size          | 512 KB        |
+
+##### Supported Hardware (see [Appendix B - Device Summary]):
+
+FP: LEDIO=0, SWIO=0
+LCD: IO=218, SIZE=20X4
+DSRTC: MODE=K80W, IO=192
+UART: IO=128
+UART: IO=136
+UART: IO=160
+UART: IO=168
+SIO MODE=STD, IO=136, CHANNEL A, INTERRUPTS ENABLED
+SIO MODE=STD, IO=136, CHANNEL B, INTERRUPTS ENABLED
+CH: IO=62
+CH: IO=60
+CHUSB: IO=62
+CHUSB: IO=60
+MD: TYPE=RAM
+MD: TYPE=ROM
+FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
+FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD
+IDE: MODE=RC, IO=16, MASTER
+IDE: MODE=RC, IO=16, SLAVE
+PPIDE: IO=32, MASTER
+PPIDE: IO=32, SLAVE
+SD: MODE=EZ512, IO=130, UNITS=1
+KIO: IO=128
+CTC: IO=132, TIMER MODE=TIMER/16, DIVISOR=9216, HI=256, LO=36, INTERRUPTS ENABLED
+
+##### Notes:
+
+- CPU speed will be dynamically measured at startup if DSRTC is present
+
+`\clearpage`{=latex}
+
 ### Z180 Z1RCC CPU Module
 
 #### ROM Image File:  RCZ180_z1rcc_std.rom

diff --git a/Source/HBIOS/Config/RCZ80_k80w_std.asm b/Source/HBIOS/Config/RCZ80_k80w_std.asm
@@ -0,0 +1,76 @@
+;
+;==================================================================================================
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 K80W
+;==================================================================================================
+;
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_MASTER.asm			- MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
+;     |
+;     +-> Config/<plt>_std.asm		- BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
+;         |
+;         +-> Config/<plt>_<cust>.asm	- USER: CUSTOM USER BUILD SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE
+#DEFINE AUTO_CMD	""		; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
+;
+#INCLUDE "Config/RCZ80_std.asm"
+;
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+;
+CPUOSC		.SET	22000000	; CPU OSC FREQ IN MHZ
+;
+KIOENABLE	.SET	TRUE		; ENABLE ZILOG KIO SUPPORT
+;
+DSRTCMODE	.SET	DSRTCMODE_K80W	; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W]
+;
+AUTOCON		.SET	FALSE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+;
+CTCENABLE	.SET	TRUE		; ENABLE ZILOG CTC SUPPORT
+CTCBASE		.SET	KIOBASE+$04	; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	TRUE		; ENABLE CTC PERIODIC TIMER
+;
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;
+SIOCNT		.SET	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIO0MODE	.SET	SIOMODE_STD	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	KIOBASE+$08	; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	1843200		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACTCC	.SET	0		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	1843200		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCTCC	.SET	1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_K80W	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY