bug fixes

Author: tinebp

hw/rtl/libs/VX_axi_adapter.sv

@@ -238,12 +238,12 @@ module VX_axi_adapter #(
             .sel_out   (arb_sel_out)
         );
 
-        // AXi write request handshake
+        // AXi request handshake
 
         wire m_axi_arvalid_w, m_axi_arready_w;
         wire m_axi_awvalid_w, m_axi_awready_w;
         wire m_axi_wvalid_w,  m_axi_wready_w;
-        reg  m_axi_aw_ack, m_axi_w_ack, axi_write_ready;
+        wire  m_axi_aw_ack, m_axi_w_ack, axi_write_ready;
 
         VX_axi_write_ack axi_write_ack (
             .clk    (clk),
@@ -261,7 +261,7 @@ module VX_axi_adapter #(
         assign m_axi_arvalid_w = arb_valid_out && ~arb_rw_out;
         assign m_axi_awvalid_w = arb_valid_out && arb_rw_out && ~m_axi_aw_ack;
         assign m_axi_wvalid_w  = arb_valid_out && arb_rw_out && ~m_axi_w_ack;
-        assign arb_ready_out = axi_write_ready || m_axi_arready_w;
+        assign arb_ready_out = arb_rw_out ? axi_write_ready : m_axi_arready_w;
 
         // AXI write address channel
 

sim/xrtsim/xrt_sim.cpp

@@ -341,7 +341,7 @@ class xrt_sim::Impl {
     for (int b = 0; b < PLATFORM_MEMORY_BANKS; ++b) {
       *m_axi_mem_[b].arready = 1;
       *m_axi_mem_[b].awready = 1;
-      *m_axi_mem_[b].wready  = 0;
+      *m_axi_mem_[b].wready  = 1;
     }
   }
 
@@ -426,6 +426,10 @@ class xrt_sim::Impl {
 
       // write response
       *m_axi_mem_[b].bvalid = 0;
+
+      // states
+      m_axi_states_[b].write_req_addr_ack = false;
+      m_axi_states_[b].write_req_data_ack = false;
     }
   }
 
@@ -479,7 +483,6 @@ class xrt_sim::Impl {
 
       // handle read requests
       if (*m_axi_mem_[b].arvalid && *m_axi_mem_[b].arready) {
-        // create read request
         auto mem_req = new mem_req_t();
         mem_req->tag   = *m_axi_mem_[b].arid;
         mem_req->addr  = uint64_t(*m_axi_mem_[b].araddr);
@@ -498,21 +501,32 @@ class xrt_sim::Impl {
         dram_queues_[b].push(mem_req);
       }
 
+      // handle write address requests
+      if (*m_axi_mem_[b].awvalid && *m_axi_mem_[b].awready && !m_axi_states_[b].write_req_addr_ack) {
+        m_axi_states_[b].write_req_addr = *m_axi_mem_[b].awaddr;
+        m_axi_states_[b].write_req_tag = *m_axi_mem_[b].awid;
+        m_axi_states_[b].write_req_addr_ack = true;
+      }
+
       // handle write data requests
-      if (*m_axi_mem_[b].wvalid && *m_axi_mem_[b].wready) {
-        // ensure write address channel is not active
-        assert(!*m_axi_mem_[b].awvalid);
+      if (*m_axi_mem_[b].wvalid && *m_axi_mem_[b].wready && !m_axi_states_[b].write_req_data_ack) {
+        m_axi_states_[b].write_req_byteen = *m_axi_mem_[b].wstrb;
+        auto data = (const uint8_t*)m_axi_mem_[b].wdata->data();
+        for (int i = 0; i < PLATFORM_MEMORY_DATA_SIZE; ++i) {
+          m_axi_states_[b].write_req_data[i] = data[i];
+        }
+        m_axi_states_[b].write_req_data_ack = true;
+      }
 
-        // capture write data
+      // handle write requests
+      if (m_axi_states_[b].write_req_addr_ack && m_axi_states_[b].write_req_data_ack) {
+        auto byteen = m_axi_states_[b].write_req_byteen;
         auto byte_addr = m_axi_states_[b].write_req_addr;
-        auto data = (const uint8_t*)m_axi_mem_[b].wdata->data();
-        auto byteen = *m_axi_mem_[b].wstrb;
         for (int i = 0; i < PLATFORM_MEMORY_DATA_SIZE; ++i) {
           if ((byteen >> i) & 0x1) {
-            (*ram_)[byte_addr + i] = data[i];
+            (*ram_)[byte_addr + i] = m_axi_states_[b].write_req_data[i];
           }
         }
-        // create write request
         auto mem_req = new mem_req_t();
         mem_req->tag   = m_axi_states_[b].write_req_tag;
         mem_req->addr  = byte_addr;
@@ -522,35 +536,29 @@ class xrt_sim::Impl {
 
         /*printf("%0ld: [sim] axi-mem-write[%d]: addr=0x%lx, byteen=0x%lx, tag=0x%x, data=0x", timestamp, b, mem_req->addr, byteen, mem_req->tag);
         for (int i = PLATFORM_MEMORY_DATA_SIZE-1; i >= 0; --i) {
-          printf("%02x", data[i]]);
+          printf("%02x", m_axi_states_[b].write_req_data[i]]);
         }
         printf("\n");*/
 
         // send dram request
         dram_queues_[b].push(mem_req);
 
-        // reset write request handshake
-        *m_axi_mem_[b].wready = 0;
-        *m_axi_mem_[b].awready = 1;
-      }
-
-      // handle write address requests
-      if (*m_axi_mem_[b].awvalid && *m_axi_mem_[b].awready) {
-        // capture write request address
-        m_axi_states_[b].write_req_addr = *m_axi_mem_[b].awaddr;
-        m_axi_states_[b].write_req_tag = *m_axi_mem_[b].awid;
-        // enable write data handshake
-        *m_axi_mem_[b].awready = 0;
-        *m_axi_mem_[b].wready = 1;
+        // clear acks
+        m_axi_states_[b].write_req_addr_ack = false;
+        m_axi_states_[b].write_req_data_ack = false;
       }
     }
   }
 
   typedef struct {
+    std::array<uint8_t, PLATFORM_MEMORY_DATA_SIZE> write_req_data;
+    uint64_t write_req_byteen;
     uint64_t write_req_addr;
     uint32_t write_req_tag;
     bool read_rsp_ready;
     bool write_rsp_ready;
+    bool write_req_addr_ack;
+    bool write_req_data_ack;
   } m_axi_state_t;
 
   typedef struct {