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bug fixes
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14 files changed

+208
-247
lines changed

14 files changed

+208
-247
lines changed

‎hw/rtl/VX_platform.vh

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -177,6 +177,9 @@
177177
`define PRESERVE_NET (* keep = "true" *)
178178
`define BLACKBOX_CELL (* black_box *)
179179
`define STRING
180+
`ifndef SIMULATION
181+
`define ASYNC_BRAM_PATCH
182+
`endif
180183
`else
181184
`define MAX_FANOUT 8
182185
`define FORCE_BRAM(d,w) (d >= 16 || w >= 128 || (d * w) >= 256)

‎hw/rtl/afu/xrt/VX_afu_wrap.sv

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -35,17 +35,21 @@ module VX_afu_wrap #(
3535
input wire s_axi_ctrl_awvalid,
3636
output wire s_axi_ctrl_awready,
3737
input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr,
38+
3839
input wire s_axi_ctrl_wvalid,
3940
output wire s_axi_ctrl_wready,
4041
input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata,
4142
input wire [C_S_AXI_CTRL_DATA_WIDTH/8-1:0] s_axi_ctrl_wstrb,
43+
4244
input wire s_axi_ctrl_arvalid,
4345
output wire s_axi_ctrl_arready,
4446
input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr,
47+
4548
output wire s_axi_ctrl_rvalid,
4649
input wire s_axi_ctrl_rready,
4750
output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata,
4851
output wire [1:0] s_axi_ctrl_rresp,
52+
4953
output wire s_axi_ctrl_bvalid,
5054
input wire s_axi_ctrl_bready,
5155
output wire [1:0] s_axi_ctrl_bresp,
@@ -69,20 +73,24 @@ module VX_afu_wrap #(
6973
wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr_a [C_M_AXI_MEM_NUM_BANKS];
7074
wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_awid_a [C_M_AXI_MEM_NUM_BANKS];
7175
wire [7:0] m_axi_mem_awlen_a [C_M_AXI_MEM_NUM_BANKS];
76+
7277
wire m_axi_mem_wvalid_a [C_M_AXI_MEM_NUM_BANKS];
7378
wire m_axi_mem_wready_a [C_M_AXI_MEM_NUM_BANKS];
7479
wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_wdata_a [C_M_AXI_MEM_NUM_BANKS];
7580
wire [C_M_AXI_MEM_DATA_WIDTH/8-1:0] m_axi_mem_wstrb_a [C_M_AXI_MEM_NUM_BANKS];
7681
wire m_axi_mem_wlast_a [C_M_AXI_MEM_NUM_BANKS];
82+
7783
wire m_axi_mem_bvalid_a [C_M_AXI_MEM_NUM_BANKS];
7884
wire m_axi_mem_bready_a [C_M_AXI_MEM_NUM_BANKS];
7985
wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_bid_a [C_M_AXI_MEM_NUM_BANKS];
8086
wire [1:0] m_axi_mem_bresp_a [C_M_AXI_MEM_NUM_BANKS];
87+
8188
wire m_axi_mem_arvalid_a [C_M_AXI_MEM_NUM_BANKS];
8289
wire m_axi_mem_arready_a [C_M_AXI_MEM_NUM_BANKS];
8390
wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_a [C_M_AXI_MEM_NUM_BANKS];
8491
wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_arid_a [C_M_AXI_MEM_NUM_BANKS];
8592
wire [7:0] m_axi_mem_arlen_a [C_M_AXI_MEM_NUM_BANKS];
93+
8694
wire m_axi_mem_rvalid_a [C_M_AXI_MEM_NUM_BANKS];
8795
wire m_axi_mem_rready_a [C_M_AXI_MEM_NUM_BANKS];
8896
wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_rdata_a [C_M_AXI_MEM_NUM_BANKS];
@@ -217,17 +225,21 @@ module VX_afu_wrap #(
217225
.s_axi_awvalid (s_axi_ctrl_awvalid),
218226
.s_axi_awready (s_axi_ctrl_awready),
219227
.s_axi_awaddr (s_axi_ctrl_awaddr),
228+
220229
.s_axi_wvalid (s_axi_ctrl_wvalid),
221230
.s_axi_wready (s_axi_ctrl_wready),
222231
.s_axi_wdata (s_axi_ctrl_wdata),
223232
.s_axi_wstrb (s_axi_ctrl_wstrb),
233+
224234
.s_axi_arvalid (s_axi_ctrl_arvalid),
225235
.s_axi_arready (s_axi_ctrl_arready),
226236
.s_axi_araddr (s_axi_ctrl_araddr),
237+
227238
.s_axi_rvalid (s_axi_ctrl_rvalid),
228239
.s_axi_rready (s_axi_ctrl_rready),
229240
.s_axi_rdata (s_axi_ctrl_rdata),
230241
.s_axi_rresp (s_axi_ctrl_rresp),
242+
231243
.s_axi_bvalid (s_axi_ctrl_bvalid),
232244
.s_axi_bready (s_axi_ctrl_bready),
233245
.s_axi_bresp (s_axi_ctrl_bresp),
@@ -428,16 +440,16 @@ module VX_afu_wrap #(
428440
always @(posedge clk) begin
429441
for (integer i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin
430442
if (m_axi_mem_awvalid_a[i] && m_axi_mem_awready_a[i]) begin
431-
`TRACE(2, ("%t: AXI Wr Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_awaddr_a[i], m_axi_mem_awid_a[i]))
443+
`TRACE(2, ("%t: AXI Wr Req [%0d]: addr=0x%0h, id=0x%0h\n", $time, i, m_axi_mem_awaddr_a[i], m_axi_mem_awid_a[i]))
432444
end
433445
if (m_axi_mem_wvalid_a[i] && m_axi_mem_wready_a[i]) begin
434-
`TRACE(2, ("%t: AXI Wr Req [%0d]: data=0x%h\n", $time, i, m_axi_mem_wdata_a[i]))
446+
`TRACE(2, ("%t: AXI Wr Req [%0d]: strb=0x%h, data=0x%h\n", $time, i, m_axi_mem_wstrb_a[i], m_axi_mem_wdata_a[i]))
435447
end
436448
if (m_axi_mem_arvalid_a[i] && m_axi_mem_arready_a[i]) begin
437-
`TRACE(2, ("%t: AXI Rd Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_araddr_a[i], m_axi_mem_arid_a[i]))
449+
`TRACE(2, ("%t: AXI Rd Req [%0d]: addr=0x%0h, id=0x%0h\n", $time, i, m_axi_mem_araddr_a[i], m_axi_mem_arid_a[i]))
438450
end
439451
if (m_axi_mem_rvalid_a[i] && m_axi_mem_rready_a[i]) begin
440-
`TRACE(2, ("%t: AXI Rd Rsp [%0d]: data=0x%h, tag=0x%0h\n", $time, i, m_axi_mem_rdata_a[i], m_axi_mem_rid_a[i]))
452+
`TRACE(2, ("%t: AXI Rd Rsp [%0d]: data=0x%h, id=0x%0h\n", $time, i, m_axi_mem_rdata_a[i], m_axi_mem_rid_a[i]))
441453
end
442454
end
443455
end

‎hw/rtl/afu/xrt/vortex_afu.v

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -40,18 +40,22 @@ module vortex_afu #(
4040
input wire s_axi_ctrl_awvalid,
4141
output wire s_axi_ctrl_awready,
4242
input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr,
43+
4344
input wire s_axi_ctrl_wvalid,
4445
output wire s_axi_ctrl_wready,
4546
input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata,
4647
input wire [C_S_AXI_CTRL_DATA_WIDTH/8-1:0] s_axi_ctrl_wstrb,
47-
input wire s_axi_ctrl_arvalid,
48+
49+
input wire s_axi_ctrl_arvalid,
4850
output wire s_axi_ctrl_arready,
4951
input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr,
52+
5053
output wire s_axi_ctrl_rvalid,
51-
input wire s_axi_ctrl_rready,
54+
input wire s_axi_ctrl_rready,
5255
output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata,
5356
output wire [1:0] s_axi_ctrl_rresp,
54-
output wire s_axi_ctrl_bvalid,
57+
58+
output wire s_axi_ctrl_bvalid,
5559
input wire s_axi_ctrl_bready,
5660
output wire [1:0] s_axi_ctrl_bresp,
5761

@@ -76,17 +80,21 @@ module vortex_afu #(
7680
.s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),
7781
.s_axi_ctrl_awready (s_axi_ctrl_awready),
7882
.s_axi_ctrl_awaddr (s_axi_ctrl_awaddr),
83+
7984
.s_axi_ctrl_wvalid (s_axi_ctrl_wvalid),
8085
.s_axi_ctrl_wready (s_axi_ctrl_wready),
8186
.s_axi_ctrl_wdata (s_axi_ctrl_wdata),
8287
.s_axi_ctrl_wstrb (s_axi_ctrl_wstrb),
88+
8389
.s_axi_ctrl_arvalid (s_axi_ctrl_arvalid),
8490
.s_axi_ctrl_arready (s_axi_ctrl_arready),
8591
.s_axi_ctrl_araddr (s_axi_ctrl_araddr),
92+
8693
.s_axi_ctrl_rvalid (s_axi_ctrl_rvalid),
8794
.s_axi_ctrl_rready (s_axi_ctrl_rready),
8895
.s_axi_ctrl_rdata (s_axi_ctrl_rdata),
8996
.s_axi_ctrl_rresp (s_axi_ctrl_rresp),
97+
9098
.s_axi_ctrl_bvalid (s_axi_ctrl_bvalid),
9199
.s_axi_ctrl_bready (s_axi_ctrl_bready),
92100
.s_axi_ctrl_bresp (s_axi_ctrl_bresp),

‎hw/rtl/cache/VX_cache_repl.sv

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,9 @@ module VX_cache_repl #(
119119
.SIZE (`CS_LINES_PER_BANK),
120120
.WRENW (LRU_WIDTH),
121121
.RDW_MODE ("R"),
122+
`ifdef SIMULATION
123+
.RESET_RAM (1),
124+
`endif
122125
.RADDR_REG (1)
123126
) plru_store (
124127
.clk (clk),
@@ -160,6 +163,9 @@ module VX_cache_repl #(
160163
.DATAW (WAY_SEL_WIDTH),
161164
.SIZE (`CS_LINES_PER_BANK),
162165
.RDW_MODE ("R"),
166+
`ifdef SIMULATION
167+
.RESET_RAM (1),
168+
`endif
163169
.RADDR_REG (1)
164170
) ctr_store (
165171
.clk (clk),

‎hw/rtl/libs/VX_axi_adapter.sv

Lines changed: 31 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -23,10 +23,10 @@ module VX_axi_adapter #(
2323
parameter NUM_PORTS_IN = 1,
2424
parameter NUM_BANKS_OUT = 1,
2525
parameter INTERLEAVE = 0,
26-
parameter TAG_BUFFER_SIZE= 32,
26+
parameter TAG_BUFFER_SIZE= 16,
2727
parameter ARBITER = "R",
28-
parameter REQ_OUT_BUF = 1,
29-
parameter RSP_OUT_BUF = 1,
28+
parameter REQ_OUT_BUF = 0,
29+
parameter RSP_OUT_BUF = 0,
3030
parameter DATA_SIZE = DATA_WIDTH/8
3131
) (
3232
input wire clk,
@@ -194,27 +194,6 @@ module VX_axi_adapter #(
194194
assign mem_req_ready[0] = arb_ready_in[req_bank_sel[0]][0];
195195
end
196196

197-
// AXi write request synchronization
198-
199-
wire [NUM_BANKS_OUT-1:0] m_axi_awvalid_w, m_axi_wvalid_w;
200-
wire [NUM_BANKS_OUT-1:0] m_axi_awready_w, m_axi_wready_w;
201-
reg [NUM_BANKS_OUT-1:0] m_axi_aw_ack, m_axi_w_ack, axi_write_ready;
202-
203-
for (genvar i = 0; i < NUM_BANKS_OUT; ++i) begin : g_axi_write_ready
204-
VX_axi_write_ack axi_write_ack (
205-
.clk (clk),
206-
.reset (reset),
207-
.awvalid(m_axi_awvalid_w[i]),
208-
.awready(m_axi_awready_w[i]),
209-
.wvalid (m_axi_wvalid_w[i]),
210-
.wready (m_axi_wready_w[i]),
211-
.aw_ack (m_axi_aw_ack[i]),
212-
.w_ack (m_axi_w_ack[i]),
213-
.tx_rdy (axi_write_ready[i]),
214-
`UNUSED_PIN (tx_ack)
215-
);
216-
end
217-
218197
// AXI request handling
219198

220199
for (genvar i = 0; i < NUM_BANKS_OUT; ++i) begin : g_axi_write_req
@@ -259,13 +238,32 @@ module VX_axi_adapter #(
259238
.sel_out (arb_sel_out)
260239
);
261240

262-
wire m_axi_arready_w;
241+
// AXi write request handshake
263242

264-
assign arb_ready_out = axi_write_ready[i] || m_axi_arready_w;
243+
wire m_axi_arvalid_w, m_axi_arready_w;
244+
wire m_axi_awvalid_w, m_axi_awready_w;
245+
wire m_axi_wvalid_w, m_axi_wready_w;
246+
reg m_axi_aw_ack, m_axi_w_ack, axi_write_ready;
265247

266-
// AXI write address channel
248+
VX_axi_write_ack axi_write_ack (
249+
.clk (clk),
250+
.reset (reset),
251+
.awvalid(m_axi_awvalid_w),
252+
.awready(m_axi_awready_w),
253+
.wvalid (m_axi_wvalid_w),
254+
.wready (m_axi_wready_w),
255+
.aw_ack (m_axi_aw_ack),
256+
.w_ack (m_axi_w_ack),
257+
.tx_rdy (axi_write_ready),
258+
`UNUSED_PIN (tx_ack)
259+
);
260+
261+
assign m_axi_arvalid_w = arb_valid_out && ~arb_rw_out;
262+
assign m_axi_awvalid_w = arb_valid_out && arb_rw_out && ~m_axi_aw_ack;
263+
assign m_axi_wvalid_w = arb_valid_out && arb_rw_out && ~m_axi_w_ack;
264+
assign arb_ready_out = axi_write_ready || m_axi_arready_w;
267265

268-
assign m_axi_awvalid_w[i] = arb_valid_out && arb_rw_out && ~m_axi_aw_ack[i];
266+
// AXI write address channel
269267

270268
VX_elastic_buffer #(
271269
.DATAW (BANK_ADDR_WIDTH + WRITE_TAG_WIDTH),
@@ -275,8 +273,8 @@ module VX_axi_adapter #(
275273
) aw_buf (
276274
.clk (clk),
277275
.reset (reset),
278-
.valid_in (m_axi_awvalid_w[i]),
279-
.ready_in (m_axi_awready_w[i]),
276+
.valid_in (m_axi_awvalid_w),
277+
.ready_in (m_axi_awready_w),
280278
.data_in ({arb_addr_out, WRITE_TAG_WIDTH'(arb_tag_out)}),
281279
.data_out ({buf_addr_w_out, buf_tag_w_out}),
282280
.valid_out (m_axi_awvalid[i]),
@@ -296,8 +294,6 @@ module VX_axi_adapter #(
296294

297295
// AXI write data channel
298296

299-
assign m_axi_wvalid_w[i] = arb_valid_out && arb_rw_out && ~m_axi_w_ack[i];
300-
301297
VX_elastic_buffer #(
302298
.DATAW (DATA_SIZE + DATA_WIDTH),
303299
.SIZE (`TO_OUT_BUF_SIZE(REQ_OUT_BUF)),
@@ -306,8 +302,8 @@ module VX_axi_adapter #(
306302
) w_buf (
307303
.clk (clk),
308304
.reset (reset),
309-
.valid_in (m_axi_wvalid_w[i]),
310-
.ready_in (m_axi_wready_w[i]),
305+
.valid_in (m_axi_wvalid_w),
306+
.ready_in (m_axi_wready_w),
311307
.data_in ({arb_byteen_out, arb_data_out}),
312308
.data_out ({m_axi_wstrb[i], m_axi_wdata[i]}),
313309
.valid_out (m_axi_wvalid[i]),
@@ -333,7 +329,7 @@ module VX_axi_adapter #(
333329
) ar_buf (
334330
.clk (clk),
335331
.reset (reset),
336-
.valid_in (arb_valid_out && ~arb_rw_out),
332+
.valid_in (m_axi_arvalid_w),
337333
.ready_in (m_axi_arready_w),
338334
.data_in ({arb_addr_out, arb_tag_r_out}),
339335
.data_out ({buf_addr_r_out, buf_tag_r_out}),

‎hw/rtl/libs/VX_axi_write_ack.sv

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -26,35 +26,35 @@ module VX_axi_write_ack (
2626
output wire tx_ack,
2727
output wire tx_rdy
2828
);
29-
reg awfired;
30-
reg wfired;
29+
reg aw_fired;
30+
reg w_fired;
3131

32-
wire awfire = awvalid && awready;
33-
wire wfire = wvalid && wready;
32+
wire aw_fire = awvalid && awready;
33+
wire w_fire = wvalid && wready;
3434

3535
always @(posedge clk) begin
3636
if (reset) begin
37-
awfired <= 0;
38-
wfired <= 0;
37+
aw_fired <= 0;
38+
w_fired <= 0;
3939
end else begin
40-
if (awfire) begin
41-
awfired <= 1;
40+
if (aw_fire) begin
41+
aw_fired <= 1;
4242
end
43-
if (wfire) begin
44-
wfired <= 1;
43+
if (w_fire) begin
44+
w_fired <= 1;
4545
end
4646
if (tx_ack) begin
47-
awfired <= 0;
48-
wfired <= 0;
47+
aw_fired <= 0;
48+
w_fired <= 0;
4949
end
5050
end
5151
end
5252

53-
assign aw_ack = awfired;
54-
assign w_ack = wfired;
53+
assign aw_ack = aw_fired;
54+
assign w_ack = w_fired;
5555

56-
assign tx_ack = (awfire || awfired) && (wfire || wfired);
57-
assign tx_rdy = (awready || awfired) && (wready || wfired);
56+
assign tx_ack = (aw_fire || aw_fired) && (w_fire || w_fired);
57+
assign tx_rdy = (awready || aw_fired) && (wready || w_fired);
5858

5959
endmodule
6060
`TRACING_ON

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