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rtl

Here are 1,030 public repositories matching this topic...

veryl

veryl-lang / veryl

Veryl: A Modern Hardware Description Language

rust rtl verilog systemverilog

Updated May 20, 2024
Rust

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

boom rocket rocket-chip chip-generator chisel riscv rtl peripherals soc out-of-order superscalar risc-v firesim accelerators chipyard hwacha

Updated May 20, 2024
Scala

sean-galloway / RTLDesignSherpa

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

rtl system-verilog uvm-verification

Updated May 19, 2024
SystemVerilog

postcss-rtlcss

elchininet / postcss-rtlcss

PostCSS plugin to automatically build Cascading Style Sheets (CSS) with Left-To-Right (LTR) and Right-To-Left (RTL) rules using RTLCSS

css plugin postcss ltr rtl postcss-plugin rtlcss arabic hebrew right-to-left left-to-right rtl-adaptivity direction postcss-rtlcss rtl-plugin automatic-rtl automatic-ltr

Updated May 20, 2024
TypeScript

Shuregg / FPGA-practicum

learning about FPGA

fpga rtl verilog xilinx vivado systemverilog fpga-programming

Updated May 19, 2024
SystemVerilog

darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cpu fpga core processor riscv rtl verilog risc-v rv32i softcore processor-design rv32e

Updated May 19, 2024
Verilog

neorv32

stnolting / neorv32

🚀 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

microcontroller embedded asic cpu fpga processor vhdl gdb riscv rtl verilog safety soc risc-v openocd soft-core system-on-chip rv32 asip neorv32

Updated May 19, 2024
VHDL

The-OpenROAD-Project / OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated May 20, 2024
Verilog

boxlambda

epsilon537 / boxlambda

FPGA based microcomputer sandbox for software and RTL experimentation

fpga retro rtl microcomputer

Updated May 19, 2024
Verilog

oscar7070 / RTLScript

RTLScript - type in Farsi, Arabic and Hebrew in C++ programs and get a fixed version of it!(forked from FarsiType)

text rtl bidirectional bidi arabic hebrew farsi

Updated May 19, 2024
C++

Chelny / e-commerce

E-commerce web application made with Next.js, TailwindCSS, Prisma and PostgresSQL

react multilingual accessibility nextjs postgresql rtl e-commerce prisma tailwindcss

Updated May 19, 2024
TypeScript

verilator

verilator / verilator

Verilator open-source SystemVerilog simulator and lint system

cpp rtl verilog compilers systemc system-verilog verilator verilog-simulator

Updated May 18, 2024
C++

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated May 18, 2024
Verilog

SpinalHDL / SpinalHDL

Scala based HDL

scala fpga vhdl rtl verilog

Updated May 18, 2024
Scala

wikimedia / language-data

Language data and utilities

ltr cldr rtl autonym

Updated May 18, 2024
PHP

chili-chips-ba / openeye-CamSI

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.

opensource video fpga camera serdes ddr raspberrypi rtl isp vlc hdmi systemverilog csi hd image-sensor uhd low-budget imx283 signal-integrity

Updated May 18, 2024
Verilog

chisel

chipsalliance / chisel

Chisel: A Modern Hardware Design Language

scala chip-generator chisel rtl chisel3 firrtl verilog

Updated May 17, 2024
Scala

riscv-boom / riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

scala berkeley boom rocket-chip chisel riscv rtl riscv-boom

Updated May 17, 2024
Scala

chipsalliance / rocket-chip

Rocket Chip Generator

scala rocket-chip chip-generator chisel riscv rtl

Updated May 17, 2024
Scala

extreme-todo / frontend

23년 안에 배포, 24년엔 리팩토링

react typescript jest emotion atomic-design rtl apex-chart

Updated May 17, 2024
TypeScript

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