hdl-util / hdmi Star 1k Code Issues Pull requests Send video/audio over HDMI on an FPGA audio video fpga intel xilinx vivado altera hdmi systemverilog dvi quartus hdlmake Updated Feb 3, 2024 SystemVerilog
kkrizka / endeavour_firmware Star 1 Code Issues Pull requests Testbench for playing with the Endeavour protocol used by AMACv2. firmware atlas testbench endeavour hdlmake Updated May 12, 2018 Verilog
tomaz-suller / PoliLEG Star 1 Code Issues Pull requests Simplified, monocycle version of the LEGv8 processor designed by PCS Poli-USP and implemented in VHDL for Digital Systems II vhdl legv8-arm hdlmake legv8 polileg Updated Jan 9, 2022 VHDL
sameer / DE2-115-template Sponsor Star 1 Code Issues Pull requests HDLMake template for terasIC DE2-115 template vhdl verilog de2-115 hdlmake Updated Feb 6, 2020 Tcl
tomaz-suller / hdlmake-template Star 1 Code Issues Pull requests Template for use with the build tool hdlmake, specifically set up for VHDL development and simulation. vhdl hdlmake Updated Jan 9, 2022 VHDL
RDSik / FPGA_transceiver Star 1 Code Issues Pull requests python vivado icarus-verilog modelsim testbench verilog-hdl cocotb hdlmake Updated May 3, 2024 Verilog
JochiSt / Nexys4-liteeth Star 0 Code Issues Pull requests use the liteeth core on the Nexys4 board without SoC vhdl nexys4 liteeth hdlmake Updated Apr 30, 2024 Tcl
RDSik / i2c_master Star 0 Code Issues Pull requests vivado icarus-verilog modelsim testbench verilog-hdl cocotb hdlmake Updated May 3, 2024 Verilog