building a computer
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Updated
Apr 25, 2019 - Assembly
building a computer
An implementation of mips architecture on FPGA using verilog
Yahtzee game designed in VHDL for Digital System Design Course in EPFL BA2 (IC Section) Grade: 88.89%
Verilog sources for Hardware Lab Assignments
Svart is an embedded (in Dart) domain-specific language for describing binary circuits, generating a strict subset of SystemVerilog and easily interacting with external tools.
Logic Analyzer IP Core
A Scheme Inspired Hardware Description Language
A compilation of several different coding challenges/exercises/drillings that I did when in my junior year. The very reason of this repo is nostalgia/documenting my first lines of code(non-projects). I might add more when seen fit.
A hardware description and simulation language that allows users to simulate the behavior of a hardware system in a easy, intuitive and fast way.
Communication of a CPLD with the analog-to-digital converter ADC0832 (modeled in VHDL)
Verilog structural model HDL program
Computer Science Master program files, assignments and projects
B.Tech CSE @ NITC
RISC-V is an open-source instruction set architecture (ISA), enabling the implementation of central processing units (CPUs) or system-on-a-chip (SoC) designs without licensing fees. This makes it highly favored among FPGA enthusiasts for softcore processor implementations.
Time domain to logarithmic frequency domain converter, as the polyphase FFT do for the linear.
Compiler for a self-invented hardware description language (mirrors https://gitlab.com/maxkl2/hdl-compiler)
This implements a simple median filter on hardware.
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