100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
makefile
verilog
synthesis
systemverilog
hdl
testbench
systemverilog-hdl
systemverilog-simulation
rtl-design
systemverilog-test-bench
edge-detector-with-mealy
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Updated
Nov 6, 2022 - SystemVerilog