A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley
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Updated
Nov 30, 2020
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compact-model
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Python version for compact model of VGSOT MTJ (Voltage Controlled Spin Orbit Torque Magnetic Tunnel Junction)
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Updated
May 9, 2021 - Python
HfO2 ferroelectric capacitor compact model for circuit simulation
eda
spice
circuit-simulation
circuit-design
electronic-design-automation
ferroelectric
compact-model
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Updated
Nov 27, 2024
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